Searched defs:insn (Results 101 - 125 of 153) sorted by relevance

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/external/google-breakpad/src/third_party/libdisasm/
H A Dia32_implicit.c377 unsigned int ia32_insn_implicit_ops( x86_insn_t *insn, unsigned int impl_idx ) { argument
397 for ( existing = insn->operands; existing; existing = existing->next ) {
406 op = x86_operand_new( insn );
411 insn->explicit_count = insn->explicit_count -1;
/external/libunwind/src/ia64/
H A DGscript.c252 script_emit (struct ia64_script *script, struct ia64_script_insn insn) argument
260 script->insn[script->count++] = insn;
269 struct ia64_script_insn insn; local
372 insn.opc = opc;
373 insn.dst = i;
374 insn.val = val;
375 script_emit (script, insn);
382 insn.opc = IA64_INSN_LOAD_PSP;
383 script_emit (script, insn);
443 struct ia64_script_insn insn; local
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/external/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp180 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
182 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
184 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
186 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
188 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
190 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
192 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
194 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
196 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
198 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
253 DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder, bool isLoad, DecodeFunc DecodeRD) argument
295 DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument
301 DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument
307 DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument
313 DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument
319 DecodeStoreInt(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument
325 DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument
331 DecodeStoreDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument
337 DecodeStoreQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument
352 DecodeCall(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument
362 DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument
369 DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument
403 DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument
431 DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument
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/external/ltrace/sysdeps/linux-gnu/arm/
H A Dtrace.c77 unsigned insn = ptrace(PTRACE_PEEKTEXT, proc->pid, local
80 if (insn == 0xef000000 || insn == 0x0f000000
81 || (insn & 0xffff0000) == 0xdf000000) {
87 } else if ((insn & 0xfff00000) == 0xef900000) {
89 *sysnum = insn & 0xfffff;
97 insn, pc);
113 arm_branch_dest(const arch_addr_t pc, const uint32_t insn) argument
116 return pc + ((((insn & 0xffffff) ^ 0x800000) - 0x800000) << 2) + 8;
288 /* Ignore if insn is
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/external/mesa3d/src/gallium/drivers/nv30/
H A Dnv30_state.h114 uint32_t *insn; member in struct:nv30_fragprog
H A Dnvfx_vertprog.c291 nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn) argument
295 unsigned slot = insn.op >> 7;
296 unsigned op = insn.op & 0x7f;
305 if (insn.cc_test != NVFX_COND_TR)
307 hw[0] |= (insn.cc_test << NVFX_VP(INST_COND_SHIFT));
308 hw[0] |= ((insn.cc_swz[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
309 (insn.cc_swz[1] << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
310 (insn.cc_swz[2] << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
311 (insn.cc_swz[3] << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
312 if(insn
465 struct nvfx_insn insn; local
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H A Dnvfx_fragprog.c83 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
90 uint32_t *hw = &fp->insn[fpc->inst_offset];
108 hw = &fp->insn[fpc->inst_offset];
112 memcpy(&fp->insn[fpc->inst_offset + 4],
121 hw = &fp->insn[fpc->inst_offset];
133 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
163 uint32_t *hw = &fp->insn[fpc->inst_offset];
189 nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn) argument
197 hw = &fp->insn[fp
241 struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none); local
444 struct nvfx_insn insn; local
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/external/mesa3d/src/gallium/drivers/nv50/codegen/
H A Dnv50_ir_build_util.h251 Instruction *insn = new_Instruction(func, op, ty); local
252 insn->setDef(0, dst);
253 insert(insn);
258 insn->fixed = 1;
259 return insn;
H A Dnv50_ir_from_tgsi.cpp44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
167 return SrcRegister(&insn->Src[s]);
173 return DstRegister(&insn->Dst[d]);
179 return SrcRegister(insn->TexOffsets[i]);
182 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
196 inline uint getLabel() { return insn->Label.Label; }
198 unsigned getSaturate() const { return insn
206 const struct tgsi_full_instruction *insn; member in class:tgsi::Instruction
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H A Dnv50_ir_build_util.cpp68 Instruction *insn = new_Instruction(func, op, ty); local
70 insn->setDef(0, dst);
71 insn->setSrc(0, src);
73 insert(insn);
74 return insn;
81 Instruction *insn = new_Instruction(func, op, ty); local
83 insn->setDef(0, dst);
84 insn->setSrc(0, src0);
85 insn->setSrc(1, src1);
87 insert(insn);
95 Instruction *insn = new_Instruction(func, op, ty); local
109 Instruction *insn = new_Instruction(func, OP_LOAD, ty); local
125 Instruction *insn = new_Instruction(func, op, ty); local
142 Instruction *insn = mkOp1(OP_VFETCH, ty, dst, sym); local
165 Instruction *insn = mkOp1(op, ty, dst, sym); local
173 Instruction *insn = new_Instruction(func, OP_MOV, ty); local
185 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(src->reg.size)); local
198 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(dst->reg.size)); local
212 Instruction *insn = new_Instruction(func, op, dstTy); local
226 CmpInstruction *insn = new_CmpInstruction(func, op); local
284 Instruction *insn = NULL; local
309 FlowInstruction *insn = new_FlowInstruction(func, op, targ); local
337 Instruction *insn = mkOp(OP_NOP, TYPE_NONE, NULL); local
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H A Dnv50_ir_from_sm4.cpp156 sm4_insn *insn; member in class:__anon12088::Converter
1141 sm4_op *op = insn->ops[s + nDstOpnds]->indices[dim].reg.get();
1161 sm4_op *op = insn->ops[d]->indices[dim].reg.get();
1179 sm4_op *op = insn->ops[s + nDstOpnds].get();
1192 return src(*insn->ops[i + nDstOpnds], c, i);
1198 return dst(*insn->ops[i], c, i);
1204 if (insn->insn.sat)
1206 return saveDst(*insn->ops[i], c, value, i);
1219 Instruction *insn
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H A Dnv50_ir_target.h166 virtual bool insnCanLoad(const Instruction *insn, int s,
178 // whether @insn can be issued together with @next (order matters)
179 virtual bool canDualIssue(const Instruction *insn, argument
213 const Target::OpInfo& Target::getOpInfo(const Instruction *insn) const
215 return opInfo[MIN2(insn->op, OP_LAST)];
H A Dnv50_ir.cpp61 ValueRef::ValueRef(Value *v) : value(NULL), insn(NULL)
69 ValueRef::ValueRef(const ValueRef& ref) : value(NULL), insn(ref.insn)
84 DataType type = src->insn->sType;
88 if (src->insn->sType != type)
101 Instruction *insn = src->value->getUniqueInsn(); local
103 if (insn && insn->op == OP_MOV) {
104 src = &insn->src(0);
114 ValueDef::ValueDef(Value *v) : value(NULL), insn(NUL
180 Instruction *insn = (*it)->getInsn(); local
1029 releaseInstruction(Instruction *insn) argument
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/external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d1x/
H A Dsm4_to_tgsi.cpp87 sm4_insn* insn; member in struct:sm4_to_tgsi_converter
129 check(i < insn->num_ops);
130 sm4_op& op = *insn->ops[i];
133 if(insn->insn.sat)
140 check(i < insn->num_ops);
141 sm4_op& op = *insn->ops[i];
189 check(i < insn->num_ops);
190 sm4_op& op = *insn->ops[i];
250 insn
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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_optimize.c634 is_single_channel_dp4(struct brw_instruction *insn) argument
636 if (insn->header.opcode != BRW_OPCODE_DP4 ||
637 insn->header.execution_size != BRW_EXECUTE_8 ||
638 insn->header.access_mode != BRW_ALIGN_16 ||
639 insn->bits1.da1.dest_reg_file != BRW_GENERAL_REGISTER_FILE)
642 if (!is_power_of_two(insn->bits1.da16.dest_writemask))
672 struct brw_instruction *insn = &p->store[i]; local
678 if (!is_single_channel_dp4(insn)) {
686 if (insn->bits1.da16.dest_writemask == prev->bits1.da16.dest_writemask)
688 if (insn
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H A Dbrw_vec4_emit.cpp663 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND); local
664 brw_set_dest(p, insn, dst);
665 brw_set_src0(p, insn, offset);
666 brw_set_sampler_message(p, insn,
H A Dbrw_wm_fp.c1027 static void print_insns( const struct prog_instruction *insn, argument
1031 for (i = 0; i < nr; i++, insn++) {
1033 if (insn->Opcode < MAX_OPCODE)
1034 _mesa_fprint_instruction_opt(stdout, insn, 0, PROG_PRINT_DEBUG, NULL);
1035 else if (insn->Opcode < MAX_WM_OPCODE) {
1036 GLuint idx = insn->Opcode - MAX_OPCODE;
1038 _mesa_fprint_alu_instruction(stdout, insn, wm_opcode_strings[idx],
1042 printf("965 Opcode %d\n", insn->Opcode);
1055 GLuint insn; local
1080 for (insn
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/external/dexmaker/src/dx/java/com/android/dx/ssa/
H A DSsaBasicBlock.java51 /** {@code non-null;} insn list associated with this instance */
199 * Adds a phi insn to the beginning of this block. The result type of
209 * Adds a phi insn to the beginning of this block. This is to be used
220 * Adds an insn to the head of this basic block, just after any phi
223 * @param insn {@code non-null;} rop-form insn to add
225 public void addInsnToHead(Insn insn) { argument
226 SsaInsn newInsn = SsaInsn.makeFromRop(insn, this);
232 * Replaces the last insn in this block. The provided insn mus
237 replaceLastInsn(Insn insn) argument
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/external/dexmaker/src/main/java/com/google/dexmaker/
H A DCode.java400 private void addInstruction(Insn insn) { argument
401 addInstruction(insn, null);
408 private void addInstruction(Insn insn, Label branch) { argument
412 currentLabel.instructions.add(insn);
414 switch (insn.getOpcode().getBranchingness()) {
/external/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp239 /// @param insn - The internal instruction.
240 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { argument
243 if (insn.mode == MODE_64BIT)
244 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI;
245 else if (insn.mode == MODE_32BIT)
246 baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI;
248 assert(insn.mode == MODE_16BIT);
249 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;
255 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
263 /// @param insn
265 translateDstIndex(MCInst &mcInst, InternalInstruction &insn) argument
287 translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis) argument
587 translateRMRegister(MCInst &mcInst, InternalInstruction &insn) argument
625 translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis) argument
808 translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis) argument
886 translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis) argument
949 translateInstruction(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis) argument
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H A DX86DisassemblerDecoder.cpp192 * @param insn - The instruction with the reader function to use. The cursor
198 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) { argument
199 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
202 ++(insn->readerCursor);
210 * @param insn - See consumeByte().
214 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) { argument
215 return insn->reader(insn
218 unconsumeByte(struct InternalInstruction* insn) argument
265 dbgprintf(struct InternalInstruction* insn, const char* format, ...) argument
292 setPrefixPresent(struct InternalInstruction* insn, uint8_t prefix, uint64_t location) argument
309 isPrefixAtLocation(struct InternalInstruction* insn, uint8_t prefix, uint64_t location) argument
326 readPrefixes(struct InternalInstruction* insn) argument
679 readOpcode(struct InternalInstruction* insn) argument
795 getIDWithAttrMask(uint16_t* instructionID, struct InternalInstruction* insn, uint16_t attrMask) argument
876 getID(struct InternalInstruction* insn, const void *miiArg) argument
1138 readSIB(struct InternalInstruction* insn) argument
1236 readDisplacement(struct InternalInstruction* insn) argument
1281 readModRM(struct InternalInstruction* insn) argument
1499 fixupReg(struct InternalInstruction *insn, const struct OperandSpecifier *op) argument
1551 readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) argument
1598 readImmediate(struct InternalInstruction* insn, uint8_t size) argument
1652 readVVVV(struct InternalInstruction* insn) argument
1682 readMaskRegister(struct InternalInstruction* insn) argument
1700 readOperands(struct InternalInstruction* insn) argument
1837 decodeInstruction( struct InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode) argument
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/external/llvm/utils/TableGen/
H A DX86RecognizableInstr.cpp192 const CodeGenInstruction &insn,
196 Rec = insn.TheDef;
230 Operands = &insn.Operands.OperandList;
266 const CodeGenInstruction &insn,
270 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
273 RecognizableInstr recogInstr(tables, insn, uid);
191 RecognizableInstr(DisassemblerTables &tables, const CodeGenInstruction &insn, InstrUID uid) argument
265 processInstr(DisassemblerTables &tables, const CodeGenInstruction &insn, InstrUID uid) argument
/external/mesa3d/src/mesa/state_tracker/
H A Dst_mesa_to_tgsi.c92 unsigned *insn; member in struct:st_translate
140 * Update the insn[] array so the next Mesa instruction points to
148 t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
149 if (t->insn == NULL) {
155 t->insn[t->insn_count++] = start;
1252 t->insn[t->labels[i].branch_target] );
1256 FREE(t->insn);
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp98 uint32_t insn,
101 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
105 uint32_t insn,
109 uint32_t insn, uint64_t Address,
112 uint32_t insn,
115 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
119 uint32_t insn, uint64_t Address,
122 uint32_t insn, uint64_t Address,
124 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
128 uint32_t insn, uint64_
732 DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
794 DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
827 DecodeUnsignedLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
888 DecodeSignedLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1073 DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1156 DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1285 DecodeAddSubERegInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1342 DecodeLogicalImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1373 DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1412 DecodeModImmTiedInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1430 DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1449 DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1485 DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1502 DecodeSystemPStateInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1523 DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
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/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp374 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
379 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
384 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
389 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
394 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
399 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
404 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
459 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, argument
464 InsnType tmp = fieldFromInstruction(insn, 17, 5);
485 tmp = fieldFromInstruction(insn,
505 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
544 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
583 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
626 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
670 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
719 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) argument
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