/external/clang/test/Index/ |
H A D | cursor-ref-names.cpp | 17 Sub inst; local 18 inst.func(); 19 inst[1]; 20 inst.operator[](1); 22 inst.Base<int>::operator[](1); 30 // CHECK: cursor-ref-names.cpp:17:9: VarDecl=inst:17:9 (Definition) Extent=[17:5 - 17:13] 35 // CHECK: cursor-ref-names.cpp:18:5: DeclRefExpr=inst:17:9 Extent=[18:5 - 18:9] 37 // CHECK: cursor-ref-names.cpp:19:5: DeclRefExpr=inst:17:9 Extent=[19:5 - 19:9] 41 // CHECK: cursor-ref-names.cpp:20:5: DeclRefExpr=inst:17:9 Extent=[20:5 - 20:9] 44 // CHECK: cursor-ref-names.cpp:22:5: DeclRefExpr=inst [all...] |
/external/llvm/lib/IR/ |
H A D | Statepoint.cpp | 31 bool llvm::isStatepoint(const Value *inst) { argument 32 if (isa<InvokeInst>(inst) || isa<CallInst>(inst)) { 33 ImmutableCallSite CS(inst); 38 bool llvm::isStatepoint(const Value &inst) { argument 39 return isStatepoint(&inst); 50 bool llvm::isGCRelocate(const Value *inst) { argument 51 if (const CallInst *call = dyn_cast<CallInst>(inst)) { 67 bool llvm::isGCResult(const Value *inst) { argument 68 if (const CallInst *call = dyn_cast<CallInst>(inst)) { [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_opcodes.c | 523 const struct rc_instruction *inst, 527 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); 574 switch (inst->U.I.TexSrcTarget) { 591 switch (inst->U.I.TexSrcTarget) { 522 rc_compute_sources_for_writemask( const struct rc_instruction *inst, unsigned int writemask, unsigned int *srcmasks) argument
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H A D | radeon_dataflow_swizzles.c | 35 struct rc_instruction * inst, unsigned src) 43 if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED) 47 c->SwizzleCaps->Split(inst->U.I.SrcReg[src], usemask, &split); 50 struct rc_instruction * mov = rc_insert_new_instruction(c, inst->Prev); 58 mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src]; 59 mov->U.I.PreSub = inst->U.I.PreSub; 79 inst->U.I.SrcReg[src].File = RC_FILE_TEMPORARY; 80 inst->U.I.SrcReg[src].Index = tempreg; 81 inst->U.I.SrcReg[src].Swizzle = 0; 82 inst 34 rewrite_source(struct radeon_compiler * c, struct rc_instruction * inst, unsigned src) argument 92 struct rc_instruction * inst; local [all...] |
H A D | radeon_pair_dead_sources.c | 20 struct rc_instruction * inst, 28 inst->U.P.RGB.Src[sub->Arg[i].Source].Used = 1; 32 inst->U.P.Alpha.Src[sub->Arg[i].Source].Used = 1; 43 struct rc_instruction * inst; local 44 for (inst = c->Program.Instructions.Next; 45 inst != &c->Program.Instructions; 46 inst = inst->Next) { 48 if (inst->Type == RC_INSTRUCTION_NORMAL) 53 inst 19 mark_used( struct rc_instruction * inst, struct rc_pair_sub_instruction * sub) argument [all...] |
H A D | radeon_rename_regs.c | 50 struct rc_instruction * inst; local 56 for(inst = c->Program.Instructions.Next; 57 inst != &c->Program.Instructions; 58 inst = inst->Next) { 59 if (inst->U.I.Opcode == RC_OPCODE_BGNLOOP)
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H A D | r3xx_fragprog.c | 57 struct rc_sub_instruction * inst = &rci->U.I; local 59 const struct rc_opcode_info *info = rc_get_opcode_info(inst->Opcode); 61 if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth) 64 if (inst->DstReg.WriteMask & RC_MASK_Z) { 65 inst->DstReg.WriteMask = RC_MASK_W; 67 inst->DstReg.WriteMask = 0; 76 inst->SrcReg[i] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[i]);
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H A D | radeon_pair_translate.c | 38 static void final_rewrite(struct rc_sub_instruction *inst) argument 42 switch(inst->Opcode) { 44 inst->SrcReg[2] = inst->SrcReg[1]; 45 inst->SrcReg[1].File = RC_FILE_NONE; 46 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111; 47 inst->SrcReg[1].Negate = RC_MASK_NONE; 48 inst->Opcode = RC_OPCODE_MAD; 51 tmp = inst->SrcReg[2]; 52 inst 87 classify_instruction(struct rc_sub_instruction * inst, int * needrgb, int * needalpha, int * istranscendent) argument 149 set_pair_instruction(struct r300_fragment_program_compiler *c, struct rc_pair_instruction * pair, struct rc_sub_instruction * inst) argument 328 check_opcode_support(struct r300_fragment_program_compiler *c, struct rc_sub_instruction *inst) argument [all...] |
/external/mesa3d/src/mesa/program/ |
H A D | program_parse_extra.c | 39 struct prog_instruction *inst) 41 inst->CondUpdate = 0; 42 inst->CondDst = 0; 43 inst->SaturateMode = SATURATE_OFF; 44 inst->Precision = FLOAT32; 53 inst->Precision = FLOAT16; 57 inst->Precision = FLOAT32; 61 inst->Precision = FIXED12; 74 inst->CondUpdate = 1; 85 inst 37 _mesa_parse_instruction_suffix(const struct asm_parser_state *state, const char *suffix, struct prog_instruction *inst) argument [all...] |
/external/mesa3d/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_tgsi_action.h | 82 const struct tgsi_full_instruction * inst; member in struct:lp_build_emit_data
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_fs_copy_propagation.cpp | 35 fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry) argument 37 if (inst->src[arg].file != entry->dst.file || 38 inst->src[arg].reg != entry->dst.reg || 39 inst->src[arg].reg_offset != entry->dst.reg_offset) { 44 if (inst->conditional_mod && 45 inst->src[arg].type == BRW_REGISTER_TYPE_UD && 51 if (intel->gen == 6 && inst->is_math() && 55 inst->src[arg].file = entry->src.file; 56 inst->src[arg].reg = entry->src.reg; 57 inst [all...] |
H A D | brw_fs_cse.cpp | 46 is_expression(const fs_inst *const inst) argument 48 switch (inst->opcode) { 90 for (fs_inst *inst = block->start; 91 inst != block->end->next; 92 inst = (fs_inst *) inst->next) { 95 if (is_expression(inst) && !inst->predicated && inst->mlen == 0 && 96 !inst [all...] |
H A D | brw_vec4_copy_propagation.cpp | 40 is_direct_copy(vec4_instruction *inst) argument 42 return (inst->opcode == BRW_OPCODE_MOV && 43 !inst->predicate && 44 inst->dst.file == GRF && 45 !inst->saturate && 46 !inst->dst.reladdr && 47 !inst->src[0].reladdr && 48 inst->dst.type == inst->src[0].type); 52 is_dominated_by_previous_instruction(vec4_instruction *inst) argument 61 try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4]) argument 163 try_copy_propagation(struct intel_context *intel, vec4_instruction *inst, int arg, src_reg *values[4]) argument 241 vec4_instruction *inst = (vec4_instruction *)node; local [all...] |
H A D | brw_wm_pass1.c | 38 struct brw_wm_instruction *inst) 42 if (inst->writemask & (1<<i)) { 43 if (!inst->dst[i]->contributes_to_output) { 44 inst->writemask &= ~(1<<i); 45 inst->dst[i] = 0; 50 return inst->writemask; 70 struct brw_wm_instruction *inst, 77 struct brw_wm_ref *ref = inst->src[arg][i]; 84 inst->src[arg][i] = NULL; 122 struct brw_wm_instruction *inst local 37 get_tracked_mask(struct brw_wm_compile *c, struct brw_wm_instruction *inst) argument 69 track_arg(struct brw_wm_compile *c, struct brw_wm_instruction *inst, GLuint arg, GLuint readmask) argument [all...] |
/external/pcre/dist/sljit/ |
H A D | sljitNativeMIPS_32.c | 352 sljit_ins *inst = (sljit_ins*)addr; local 354 inst[0] = (inst[0] & 0xffff0000) | ((new_addr >> 16) & 0xffff); 355 inst[1] = (inst[1] & 0xffff0000) | (new_addr & 0xffff); 356 SLJIT_CACHE_FLUSH(inst, inst + 2); 361 sljit_ins *inst = (sljit_ins*)addr; local 363 inst[0] = (inst[ [all...] |
H A D | sljitNativePPC_32.c | 255 sljit_ins *inst = (sljit_ins*)addr; local 257 inst[0] = (inst[0] & 0xffff0000) | ((new_addr >> 16) & 0xffff); 258 inst[1] = (inst[1] & 0xffff0000) | (new_addr & 0xffff); 259 SLJIT_CACHE_FLUSH(inst, inst + 2); 264 sljit_ins *inst = (sljit_ins*)addr; local 266 inst[0] = (inst[ [all...] |
H A D | sljitNativeSPARC_32.c | 150 sljit_ins *inst = (sljit_ins*)addr; local 152 inst[0] = (inst[0] & 0xffc00000) | ((new_addr >> 10) & 0x3fffff); 153 inst[1] = (inst[1] & 0xfffffc00) | (new_addr & 0x3ff); 154 SLJIT_CACHE_FLUSH(inst, inst + 2); 159 sljit_ins *inst = (sljit_ins*)addr; local 161 inst[0] = (inst[ [all...] |
/external/lldb/include/lldb/Core/ |
H A D | Opcode.h | 46 Opcode (uint8_t inst) : m_type (eType8) argument 48 m_data.inst8 = inst; 51 Opcode (uint16_t inst) : m_type (eType16) argument 53 m_data.inst16 = inst; 56 Opcode (uint32_t inst) : m_type (eType32) argument 58 m_data.inst32 = inst; 61 Opcode (uint64_t inst) : m_type (eType64) argument 63 m_data.inst64 = inst; 148 SetOpcode8 (uint8_t inst) argument 151 m_data.inst8 = inst; 155 SetOpcode16(uint16_t inst) argument 162 SetOpcode16_2(uint32_t inst) argument 169 SetOpcode32(uint32_t inst) argument 176 SetOpcode64(uint64_t inst) argument [all...] |
/external/lldb/source/API/ |
H A D | SBInstructionList.cpp | 60 SBInstruction inst; local 62 inst.SetOpaque (m_opaque_sp->GetInstructionList().GetInstructionAtIndex (idx)); 63 return inst; 105 Instruction *inst = m_opaque_sp->GetInstructionList().GetInstructionAtIndex (i).get(); local 106 if (inst == NULL) 108 inst->Dump (&sref, max_opcode_byte_size, true, false, NULL);
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/external/lldb/source/Plugins/Disassembler/llvm/ |
H A D | DisassemblerLLVMC.h | 142 void Lock(InstructionLLVMC *inst, argument 146 m_inst = inst;
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/external/ltrace/sysdeps/linux-gnu/arm/ |
H A D | regs.c | 72 arm_get_shifted_register(struct process *proc, uint32_t inst, int carry, argument 75 enum arm_register rm = BITS(inst, 0, 3); 76 unsigned long shifttype = BITS(inst, 5, 6); 79 if (BIT(inst, 4)) { 80 if (arm_get_register_offpc(proc, BITS(inst, 8, 11), &shift) < 0) 84 shift = BITS(inst, 7, 11); 90 res = (uintptr_t)pc_val + (BIT(inst, 4) ? 12 : 8);
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/external/mesa3d/src/gallium/auxiliary/tgsi/ |
H A D | tgsi_parse.c | 184 struct tgsi_full_instruction *inst = &ctx->FullToken.FullInstruction; local 186 memset(inst, 0, sizeof *inst); 187 copy_token(&inst->Instruction, &token); 189 if (inst->Instruction.Predicate) { 190 next_token(ctx, &inst->Predicate); 193 if (inst->Instruction.Label) { 194 next_token( ctx, &inst->Label); 197 if (inst->Instruction.Texture) { 198 next_token( ctx, &inst [all...] |
H A D | tgsi_transform.c | 42 const struct tgsi_full_instruction *inst) 46 ti += tgsi_build_full_instruction(inst, 41 emit_instruction(struct tgsi_transform_context *ctx, const struct tgsi_full_instruction *inst) argument
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H A D | tgsi_util.c | 172 tgsi_util_get_inst_usage_mask(const struct tgsi_full_instruction *inst, argument 175 const struct tgsi_full_src_register *src = &inst->Src[src_idx]; 176 unsigned write_mask = inst->Dst[0].Register.WriteMask; 181 switch (inst->Instruction.Opcode) { 266 switch (inst->Texture.Texture) { 297 if (inst->Instruction.Opcode != TGSI_OPCODE_TEX) {
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/external/mesa3d/src/gallium/drivers/nv30/ |
H A D | nv30_vertprog.c | 90 uint32_t *inst, target; local 106 inst = vp->insns[reloc->location].data; 109 inst[2] &= ~0x000007fc; 110 inst[2] |= target << 2; 115 inst = vp->insns[reloc->location].data; 118 inst[2] &= ~0x0000003f; 119 inst[2] |= target >> 3; 120 inst[3] &= ~0xe0000000; 121 inst[3] |= target << 29; 133 uint32_t *inst, targe local [all...] |