| /external/llvm/include/llvm/MC/ |
| H A D | MachineLocation.h | 53 bool isReg() const { return IsRegister; } function
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| H A D | MCInst.h | 56 bool isReg() const { return Kind == kRegister; } function in class:llvm::MCOperand
64 assert(isReg() && "This is not a register operand!");
70 assert(isReg() && "This is not a register operand!");
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| /external/llvm/lib/Target/Mips/InstPrinter/ |
| H A D | MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) { function
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
191 if (Op.isReg()) {
296 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
298 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
301 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
304 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
307 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
310 return isReg<Mip
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 191 return isReg() ? 0 : SubReg_TargetFlags;
194 assert(!isReg() && "Register operands can't have target flags");
199 assert(!isReg() && "Register operands can't have target flags");
226 /// isReg - Tests if this is a MO_Register operand.
227 bool isReg() const { return OpKind == MO_Register; } function in class:llvm::MachineOperand
265 assert(isReg() && "This is not a register operand!");
270 assert(isReg() && "Wrong MachineOperand accessor");
275 assert(isReg() && "Wrong MachineOperand accessor");
280 assert(isReg() && "Wrong MachineOperand accessor");
285 assert(isReg()
[all...] |
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenInstruction.h | 323 bool isReg() const { return Kind == K_Reg; } function in struct:llvm::CodeGenInstAlias::ResultOperand
328 Record *getRegister() const { assert(isReg()); return R; }
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 532 if (MO.isReg()) {
690 if (MCOp1.isImm() && MCOp2.isReg() &&
890 if (!MO.isReg()) {
974 if (!MO.isReg()) {
1133 bool isReg = MO.getReg() != 0; local
1136 if (isReg) {
1142 return Binary | (isAdd << 12) | (isReg << 13);
1191 if (!MO.isReg()) {
1267 if (!MO.isReg()) {
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 250 bool isReg() const { return Kind == CV_Register; } function in class:__anon10723::CountValue
254 assert(isReg() && "Wrong CountValue accessor");
258 assert(isReg() && "Wrong CountValue accessor");
267 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
522 if (Op1.isReg()) {
559 if (InitialValue->isReg()) {
586 if (InitialValue->isReg()) {
593 if (EndValue->isReg()) {
619 if (Start->isReg()) {
624 if (End->isReg()) {
[all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 191 bool isReg() const override {
194 bool isReg(RegisterKind RegKind) const { function in class:__anon10877::SystemZOperand
294 bool isGR32() const { return isReg(GR32Reg); }
295 bool isGRH32() const { return isReg(GRH32Reg); }
297 bool isGR64() const { return isReg(GR64Reg); }
298 bool isGR128() const { return isReg(GR128Reg); }
299 bool isADDR32() const { return isReg(ADDR32Reg); }
300 bool isADDR64() const { return isReg(ADDR64Reg); }
302 bool isFP32() const { return isReg(FP32Reg); }
303 bool isFP64() const { return isReg(FP64Re
[all...] |
| /external/valgrind/VEX/priv/ |
| H A D | guest_x86_toIR.c | 5562 Bool isReg = epartIsReg(modrm); local
5655 if (isReg) {
5693 ( isReg ? nameMMXReg(eregOfRM(modrm)) : dis_buf ),
6460 Bool isReg; local
6476 isReg = epartIsReg(modrm);
6477 if (isReg) {
6489 ( isReg ? nameIReg(sz, eregOfRM(modrm)) : dis_buf ),
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| H A D | guest_amd64_toIR.c | 7045 Bool isReg = epartIsReg(modrm); local
7138 if (isReg) {
7176 ( isReg ? nameMMXReg(eregLO3ofRM(modrm)) : dis_buf ),
8121 Bool isReg; local
8135 isReg = epartIsReg(modrm);
8136 if (isReg) {
8148 ( isReg ? nameIRegE(sz, pfx, modrm) : dis_buf ),
[all...] |