Searched defs:mir (Results 1 - 25 of 36) sorted by relevance

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/art/compiler/dex/
H A Dpost_opt_passes.cc30 MIR* mir = bb->first_mir_insn; local
32 while (mir != nullptr) {
33 MIR* next = mir->next;
35 Instruction::Code opcode = mir->dalvikInsn.opcode;
38 bb->RemoveMIR(mir);
41 mir = next;
H A Dgvn_dead_code_elimination.h63 : mir(m), uses_all_vregs(false), must_keep(false), is_move(false), is_move_src(false),
73 MIR* mir; member in struct:art::GvnDeadCodeElimination::MIRData
74 bool uses_all_vregs : 1; // If mir uses all vregs, uses in mir->ssa_rep are irrelevant.
93 void AddMIRWithDef(MIR* mir, int v_reg, bool wide, uint16_t new_value);
94 void AddMIRWithoutDef(MIR* mir);
132 static void KillMIR(MIR* mir);
133 static void ChangeBinOp2AddrToPlainBinOp(MIR* mir);
149 bool RecordMIR(MIR* mir);
H A Dmir_dataflow.cc986 MIR* mir; local
998 for (mir = bb->first_mir_insn; mir != nullptr; mir = mir->next) {
999 uint64_t df_attributes = GetDataFlowAttributes(mir);
1000 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
1039 HandleExtended(use_v, def_v, live_in_v, mir->dalvikInsn);
1075 void MIRGraph::AllocateSSAUseData(MIR *mir, int num_uses) { argument
1076 mir
1083 AllocateSSADefData(MIR *mir, int num_defs) argument
1092 DataFlowSSAFormat35C(MIR* mir) argument
1105 DataFlowSSAFormat3RC(MIR* mir) argument
1117 DataFlowSSAFormatExtended(MIR* mir) argument
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H A Dglobal_value_numbering.h127 uint16_t GetIFieldId(MIR* mir) { argument
128 return GetMirGraph()->GetGvnIFieldId(mir);
132 uint16_t GetSFieldId(MIR* mir) { argument
133 return GetMirGraph()->GetGvnSFieldId(mir);
H A Dlocal_value_numbering_test.cc143 MIR* mir = &mirs_[i]; local
144 mir->dalvikInsn.opcode = def->opcode;
145 mir->dalvikInsn.vB = static_cast<int32_t>(def->value);
146 mir->dalvikInsn.vB_wide = def->value;
149 mir->meta.ifield_lowering_info = def->field_info;
154 mir->meta.sfield_lowering_info = def->field_info;
158 mir->ssa_rep = &ssa_reps_[i];
159 mir->ssa_rep->num_uses = def->num_uses;
160 mir->ssa_rep->uses = const_cast<int32_t*>(def->uses); // Not modified by LVN.
161 mir
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H A Dmir_optimization_test.cc287 MIR* mir = &mirs_[i]; local
288 mir->dalvikInsn.opcode = def->opcode;
291 bb->AppendMIR(mir);
294 mir->meta.ifield_lowering_info = def->field_or_method_info;
299 mir->meta.sfield_lowering_info = def->field_or_method_info;
304 mir->meta.method_lowering_info = def->field_or_method_info;
306 mir->dalvikInsn.vA = def->vA;
307 mir->dalvikInsn.vB = def->vB;
308 mir->dalvikInsn.vC = def->vC;
309 mir
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H A Dglobal_value_numbering_test.cc236 MIR* mir = &mirs_[i]; local
239 bb->AppendMIR(mir);
240 mir->dalvikInsn.opcode = def->opcode;
241 mir->dalvikInsn.vB = static_cast<int32_t>(def->value);
242 mir->dalvikInsn.vB_wide = def->value;
245 mir->meta.ifield_lowering_info = def->field_info;
250 mir->meta.sfield_lowering_info = def->field_info;
254 mir->meta.phi_incoming =
257 std::copy(bb->predecessors.begin(), bb->predecessors.end(), mir->meta.phi_incoming);
259 mir
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H A Dgvn_dead_code_elimination.cc90 void GvnDeadCodeElimination::VRegChains::AddMIRWithDef(MIR* mir, int v_reg, bool wide, argument
93 mir_data_.emplace_back(mir);
122 inline void GvnDeadCodeElimination::VRegChains::AddMIRWithoutDef(MIR* mir) { argument
123 mir_data_.emplace_back(mir);
152 DCHECK_EQ(static_cast<int>(last_data->mir->dalvikInsn.opcode), static_cast<int>(kMirOpNop));
365 SSARepresentation* ssa_rep = mir_data_[c].mir->ssa_rep;
380 SSARepresentation* ssa_rep = mir_data_[c].mir->ssa_rep;
393 SSARepresentation* ssa_rep = mir_data_[c].mir->ssa_rep;
411 MIR* mir = mir_data_[c].mir; local
508 KillMIR(MIR* mir) argument
514 ChangeBinOp2AddrToPlainBinOp(MIR* mir) argument
1036 RecordMIR(MIR* mir) argument
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H A Dgvn_dead_code_elimination_test.cc264 MIR* mir = &mirs_[i]; local
267 bb->AppendMIR(mir);
268 mir->dalvikInsn.opcode = def->opcode;
269 mir->dalvikInsn.vB = static_cast<int32_t>(def->value);
270 mir->dalvikInsn.vB_wide = def->value;
273 mir->meta.ifield_lowering_info = def->field_info;
278 mir->meta.sfield_lowering_info = def->field_info;
282 mir->meta.phi_incoming =
285 std::copy(bb->predecessors.begin(), bb->predecessors.end(), mir->meta.phi_incoming);
287 mir
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H A Dtype_inference.cc317 void TypeInference::CheckCastData::ProcessCheckCast(MIR* mir) { argument
318 auto mir_it = check_cast_map_.find(mir);
320 auto sreg_it = split_sreg_data_.find(mir->ssa_rep->uses[0]);
423 MIR* mir = bb->first_mir_insn; local
425 for (; mir != main_mirs_end && static_cast<int>(mir->dalvikInsn.opcode) == kMirOpPhi;
426 mir = mir->next) {
430 size_t num_uses = mir->ssa_rep->num_uses;
431 const int32_t* uses = mir
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H A Dtype_inference_test.cc390 MIR* mir = &mirs_[i]; local
393 bb->AppendMIR(mir);
394 mir->dalvikInsn.opcode = def->opcode;
395 mir->dalvikInsn.vB = static_cast<int32_t>(def->value);
396 mir->dalvikInsn.vB_wide = def->value;
399 mir->meta.ifield_lowering_info = def->metadata;
405 mir->meta.sfield_lowering_info = def->metadata;
411 mir->meta.method_lowering_info = def->metadata;
412 mir->dalvikInsn.vA = def->num_uses;
415 mir
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/art/compiler/dex/quick/mips/
H A Dfp_mips.cc257 void MipsMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) { argument
258 UNUSED(bb, mir, gt_bias, is_double);
H A Dcall_mips.cc35 bool MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special) { argument
37 UNUSED(bb, mir, special);
72 void MipsMir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { argument
73 const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
77 tab_rec->switch_mir = mir;
145 void MipsMir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { argument
146 const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
150 tab_rec->switch_mir = mir;
H A Dint_mips.cc293 void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { argument
294 UNUSED(bb, mir);
298 void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { argument
299 UNUSED(bb, mir);
/art/compiler/dex/quick/x86/
H A Dquick_assemble_x86_test.cc202 MIR* mir = cu_->mir_graph->NewMIR(); local
203 mir->dalvikInsn.opcode = opcode;
204 mir->dalvikInsn.vA = 0; // Destination and source.
205 mir->dalvikInsn.vB = 1; // Source.
208 mir->dalvikInsn.vC = (vector_type << 16) | vector_size; // Type size.
209 (m2l->*f)(mir);
H A Dcall_x86.cc38 void X86Mir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { argument
39 GenSmallSparseSwitch(mir, table_offset, rl_src);
58 void X86Mir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { argument
59 const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
63 tab_rec->switch_mir = mir;
H A Dfp_x86.cc512 void X86Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, argument
520 rl_src1 = mir_graph_->GetSrcWide(mir, 0);
521 rl_src2 = mir_graph_->GetSrcWide(mir, 2);
526 rl_src1 = mir_graph_->GetSrc(mir, 0);
527 rl_src2 = mir_graph_->GetSrc(mir, 1);
532 ConditionCode ccode = mir->meta.ccode;
H A Dutility_x86.cc957 void X86Mir2Lir::AnalyzeMIR(RefCounts* core_counts, MIR* mir, uint32_t weight) { argument
959 Mir2Lir::AnalyzeMIR(core_counts, mir, weight);
963 int opcode = mir->dalvikInsn.opcode;
982 uses_pc_rel_load = AnalyzeFPInstruction(opcode, mir);
987 if (mir_graph_->GetTable(mir, mir->dalvikInsn.vB)[1] > kSmallSwitchThreshold) {
1001 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1010 if (mir_graph_->GetMethodLoweringInfo(mir).IsIntrinsic()) {
1011 uses_pc_rel_load = AnalyzeInvokeStaticIntrinsic(mir);
1016 Mir2Lir::AnalyzeMIR(core_counts, mir, weigh
1026 AnalyzeFPInstruction(int opcode, MIR* mir) argument
1067 AnalyzeInvokeStaticIntrinsic(MIR* mir) argument
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/art/compiler/dex/quick/arm/
H A Dfp_arm.cc245 void ArmMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, argument
251 rl_src1 = mir_graph_->GetSrcWide(mir, 0);
252 rl_src2 = mir_graph_->GetSrcWide(mir, 2);
257 rl_src1 = mir_graph_->GetSrc(mir, 0);
258 rl_src2 = mir_graph_->GetSrc(mir, 1);
264 ConditionCode ccode = mir->meta.ccode;
H A Dcall_arm.cc56 void ArmMir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { argument
57 const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
61 tab_rec->switch_mir = mir;
101 void ArmMir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { argument
102 const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
106 tab_rec->switch_mir = mir;
H A Dtarget_arm.cc990 void ArmMir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { argument
992 DCHECK(MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode));
996 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
998 rl_dest = mir_graph_->GetDest(mir);
999 rl_src[0] = mir_graph_->GetSrc(mir, 0);
1000 rl_src[1] = mir_graph_->GetSrc(mir, 1);
1001 rl_src[2]= mir_graph_->GetSrc(mir, 2);
1005 rl_dest = mir_graph_->GetDest(mir);
1006 rl_src[0] = mir_graph_->GetSrc(mir, 0);
1007 rl_src[1] = mir_graph_->GetSrc(mir,
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/art/compiler/dex/quick/arm64/
H A Dfp_arm64.cc229 void Arm64Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, argument
235 rl_src1 = mir_graph_->GetSrcWide(mir, 0);
236 rl_src2 = mir_graph_->GetSrcWide(mir, 2);
241 rl_src1 = mir_graph_->GetSrc(mir, 0);
242 rl_src2 = mir_graph_->GetSrc(mir, 1);
247 ConditionCode ccode = mir->meta.ccode;
H A Dcall_arm64.cc55 void Arm64Mir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { argument
56 const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
60 tab_rec->switch_mir = mir;
104 void Arm64Mir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { argument
105 const uint16_t* table = mir_graph_->GetTable(mir, table_offset);
109 tab_rec->switch_mir = mir;
H A Dtarget_arm64.cc885 void Arm64Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { argument
887 DCHECK(MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode));
891 ExtendedMIROpcode opcode = static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode);
895 rl_dest = mir_graph_->GetDest(mir);
896 rl_src[0] = mir_graph_->GetSrc(mir, 0);
897 rl_src[1] = mir_graph_->GetSrc(mir, 1);
898 rl_src[2]= mir_graph_->GetSrc(mir, 2);
903 rl_dest = mir_graph_->GetDestWide(mir);
904 rl_src[0] = mir_graph_->GetSrcWide(mir, 0);
905 rl_src[1] = mir_graph_->GetSrcWide(mir,
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/art/compiler/dex/quick/
H A Dmir_to_lir.cc242 bool Mir2Lir::GenSpecialIGet(MIR* mir, const InlineMethod& special) { argument
284 GenPrintLabel(mir);
310 bool Mir2Lir::GenSpecialIPut(MIR* mir, const InlineMethod& special) { argument
358 GenPrintLabel(mir);
374 bool Mir2Lir::GenSpecialIdentity(MIR* mir, const InlineMethod& special) { argument
384 GenPrintLabel(mir);
394 bool Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special) { argument
396 current_dalvik_offset_ = mir->offset;
405 DCHECK_EQ(mir->dalvikInsn.opcode, Instruction::RETURN_VOID);
409 return_mir = mir;
476 CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list) argument
1136 HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir) argument
1200 GenPrintLabel(MIR* mir) argument
1212 MIR* mir; local
1317 MIR* mir = bb->first_mir_insn; local
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