/art/tools/dexfuzz/src/dexfuzz/rawdex/ |
H A D | OpcodeInfo.java | 27 public final Opcode opcode; field in class:OpcodeInfo 35 public OpcodeInfo(Opcode opcode, String name, int opcodeValue, AbstractFormat fmt) { argument 36 this.opcode = opcode;
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H A D | Instruction.java | 117 // Remember the offset, so after reading the opcode, we can read the whole 123 Log.errorAndQuit("Couldn't find OpcodeInfo for opcode with value: " 170 int opcode = (firstCodeWord & 0xff); 172 if (opcode == 0x0 && upperBits != 0x0) { 193 return opcode; 300 public static OpcodeInfo getOpcodeInfo(Opcode opcode) { argument 301 return opcode_map_by_enum.get(opcode); 308 private static void addOpcodeInfo(Opcode opcode, String name, argument 310 OpcodeInfo info = new OpcodeInfo(opcode, name, opcodeValue, fmt); 311 if (opcode [all...] |
/art/compiler/dex/ |
H A D | post_opt_passes.cc | 35 Instruction::Code opcode = mir->dalvikInsn.opcode; local 37 if (opcode == static_cast<Instruction::Code> (kMirOpPhi)) {
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H A D | local_value_numbering_test.cc | 46 Instruction::Code opcode; member in struct:art::LocalValueNumberingTest::MIRDef 55 #define DEF_CONST(opcode, reg, value) \ 56 { opcode, value, 0u, 0, { }, 1, { reg } } 57 #define DEF_CONST_WIDE(opcode, reg, value) \ 58 { opcode, value, 0u, 0, { }, 2, { reg, reg + 1 } } 59 #define DEF_CONST_STRING(opcode, reg, index) \ 60 { opcode, index, 0u, 0, { }, 1, { reg } } 61 #define DEF_IGET(opcode, reg, obj, field_info) \ 62 { opcode, 0u, field_info, 1, { obj }, 1, { reg } } 63 #define DEF_IGET_WIDE(opcode, re [all...] |
H A D | mir_optimization_test.cc | 54 Instruction::Code opcode; member in struct:art::MirOptimizationTest::MIRDef 84 #define DEF_SGET_SPUT(bb, opcode, vA, field_info) \ 85 { bb, opcode, field_info, vA, 0u, 0u } 86 #define DEF_IGET_IPUT(bb, opcode, vA, vB, field_info) \ 87 { bb, opcode, field_info, vA, vB, 0u } 88 #define DEF_AGET_APUT(bb, opcode, vA, vB, vC) \ 89 { bb, opcode, 0u, vA, vB, vC } 90 #define DEF_INVOKE(bb, opcode, vC, method_info) \ 91 { bb, opcode, method_info, 0u, 0u, vC } 92 #define DEF_OTHER0(bb, opcode) \ [all...] |
/art/compiler/dex/quick/mips/ |
H A D | fp_mips.cc | 26 void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, argument 35 switch (opcode) { 63 LOG(FATAL) << "Unexpected opcode: " << opcode; 72 void MipsMir2Lir::GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, argument 77 switch (opcode) { 105 LOG(FATAL) << "Unpexpected opcode: " << opcode; 132 void MipsMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, argument 136 switch (opcode) { 208 GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument [all...] |
H A D | assemble_mips.cc | 29 * opcode: MipsOpCode enum 30 * skeleton: pre-designated bit-pattern for this opcode 44 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \ 47 {k3, k3s, k3e}}, opcode, flags, name, fmt, size} 595 int opcode = lir->opcode; local 597 switch (opcode) { 604 case kMipsBeq: opcode = kMipsBne; break; 605 case kMipsBne: opcode = kMipsBeq; break; 606 case kMipsBeqz: opcode [all...] |
H A D | utility_mips.cc | 33 int opcode; local 39 opcode = kMipsFmovd; 45 opcode = kMips64Dmtc1; 49 opcode = kMips64Dmfc1; 54 opcode = kMipsFmovs; 60 opcode = kMipsMtc1; 64 opcode = kMipsMfc1; 71 opcode = kMipsFmovd; 75 opcode = kMipsFmovs; 81 opcode 281 MipsOpCode opcode = kMipsNop; local 305 MipsOpCode opcode = kMipsNop; local 348 MipsOpCode opcode = kMipsNop; local 467 MipsOpCode opcode = kMipsNop; local 573 MipsOpCode opcode = kMipsNop; local 646 MipsOpCode opcode = kMipsNop; local 703 MipsOpCode opcode = kMipsNop; local 880 MipsOpCode opcode = kMipsNop; local [all...] |
/art/compiler/dex/quick/x86/ |
H A D | quick_assemble_x86_test.cc | 138 int opcode, int op0 = 0, int op1 = 0, int op2 = 0, int op3 = 0, int op4 = 0) { 143 lir.opcode = opcode; 196 Instruction::Code opcode, 203 mir->dalvikInsn.opcode = opcode; 137 Test(InstructionSet target, std::string test_name, std::string gcc_asm, int opcode, int op0 = 0, int op1 = 0, int op2 = 0, int op3 = 0, int op4 = 0) argument 195 TestVectorFn(InstructionSet target, Instruction::Code opcode, AsmFn f, std::string inst_string) argument
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H A D | fp_x86.cc | 26 void X86Mir2Lir::GenArithOpFloat(Instruction::Code opcode, argument 35 switch (opcode) { 60 LOG(FATAL) << "Unexpected opcode: " << opcode; 77 void X86Mir2Lir::GenArithOpDouble(Instruction::Code opcode, argument 88 switch (opcode) { 113 LOG(FATAL) << "Unexpected opcode: " << opcode; 176 int opcode = is_double ? kX86Fstp64M : kX86Fstp32M; local 178 LIR *fstp = NewLIR2NoDest(opcode, rs_rX86_SP_3 210 GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) argument 439 int opcode = is_double ? kX86Fst64M : kX86Fst32M; local [all...] |
/art/disassembler/ |
H A D | disassembler_mips.cc | 328 std::string opcode; local 334 opcode = StringPrintf("op=%d fn=%d", op, function); 338 opcode = gMipsInstructions[i].name; 369 case 0: opcode += ".s"; break; 370 case 1: opcode += ".d"; break; 371 case 4: opcode += ".w"; break; 372 case 5: opcode += ".l"; break; 373 case 6: opcode += ".ps"; break; 374 default: opcode += ".?"; break; 447 << StringPrintf(": %08x\t%-7s ", instruction, opcode [all...] |
/art/runtime/ |
H A D | dex_instruction.cc | 63 #define INSTRUCTION_SIZE(opcode, c, p, format, r, i, a, v) \ 64 ((opcode == NOP) ? -1 : \ 93 Code opcode = static_cast<Code>(insn & 0xFF); local 94 return FlagsOf(opcode) & Instruction::kContinue; 156 const char* opcode = kInstructionNames[Opcode()]; local 158 case k10x: os << opcode; break; local 159 case k12x: os << StringPrintf("%s v%d, v%d", opcode, VRegA_12x(), VRegB_12x()); break; 160 case k11n: os << StringPrintf("%s v%d, #%+d", opcode, VRegA_11n(), VRegB_11n()); break; 161 case k11x: os << StringPrintf("%s v%d", opcode, VRegA_11x()); break; 162 case k10t: os << StringPrintf("%s %+d", opcode, VRegA_10 332 os << opcode << " {"; local 349 os << opcode << " {"; local 363 os << opcode << " {"; local [all...] |
H A D | dex_instruction_utils.h | 52 constexpr bool IsInstructionReturn(Instruction::Code opcode) { argument 53 return Instruction::RETURN_VOID <= opcode && opcode <= Instruction::RETURN_OBJECT; 56 constexpr bool IsInstructionInvoke(Instruction::Code opcode) { argument 57 return Instruction::INVOKE_VIRTUAL <= opcode && opcode <= Instruction::INVOKE_INTERFACE_RANGE && 58 opcode != Instruction::RETURN_VOID_NO_BARRIER; 61 constexpr bool IsInstructionQuickInvoke(Instruction::Code opcode) { argument 62 return opcode == Instruction::INVOKE_VIRTUAL_QUICK || 63 opcode 66 IsInstructionInvokeStatic(Instruction::Code opcode) argument 70 IsInstructionGoto(Instruction::Code opcode) argument 74 IsInstructionIfCc(Instruction::Code opcode) argument 78 IsInstructionIfCcZ(Instruction::Code opcode) argument 129 IsInvokeInstructionRange(Instruction::Code opcode) argument 136 InvokeInstructionType(Instruction::Code opcode) argument [all...] |
/art/compiler/dex/quick/arm/ |
H A D | assemble_arm.cc | 27 * opcode: ArmOpcode enum 28 * skeleton: pre-designated bit-pattern for this opcode 42 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \ 45 {k3, k3s, k3e}}, opcode, flags, name, fmt, size, fixup} 1090 int opcode = lir->opcode; local 1091 if (IsPseudoLirOp(opcode)) { 1092 if (UNLIKELY(opcode == kPseudoPseudoAlign4)) { 1093 // Note: size for this opcode will be either 0 or 2 depending on final alignment. 1101 const ArmEncodingMap *encoder = &EncodingMap[lir->opcode]; [all...] |
H A D | fp_arm.cc | 26 void ArmMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, argument 35 switch (opcode) { 63 LOG(FATAL) << "Unexpected opcode: " << opcode; 72 void ArmMir2Lir::GenArithOpDouble(Instruction::Code opcode, argument 77 switch (opcode) { 105 LOG(FATAL) << "Unexpected opcode: " << opcode; 145 void ArmMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) { argument 150 switch (opcode) { 296 GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument [all...] |
H A D | utility_arm.cc | 138 bool ArmMir2Lir::InexpensiveConstantInt(int32_t value, Instruction::Code opcode) { argument 139 switch (opcode) { 271 ArmOpcode opcode = kThumbBkpt; local 274 opcode = kThumbBlxR; 277 opcode = kThumbBx; 280 LOG(FATAL) << "Bad opcode " << op; 282 return NewLIR1(opcode, r_dest_src.GetReg()); 289 ArmOpcode opcode = kThumbBkpt; local 292 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR; 295 opcode 442 ArmOpcode opcode = kThumbBkpt; local 516 ArmOpcode opcode = kThumbBkpt; local 660 ArmOpcode opcode = kThumbBkpt; local 752 ArmOpcode opcode = kThumbBkpt; local 818 ArmOpcode opcode = kThumbBkpt; local 880 LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base, int displacement, RegStorage r_src_dest, RegStorage r_work) argument 1227 int opcode; local [all...] |
/art/compiler/dex/quick/arm64/ |
H A D | assemble_arm64.cc | 55 * opcode: A64Opcode enum 65 #define ENCODING_MAP(opcode, variants, a0k, a0s, a0e, a1k, a1s, a1e, a2k, a2s, a2e, \ 68 {a3k, a3s, a3e}}, opcode, flags, name, fmt, 4, fixup} 692 bool opcode_is_wide = IS_WIDE(lir->opcode); 693 A64Opcode opcode = UNWIDE(lir->opcode); local 695 if (UNLIKELY(IsPseudoLirOp(opcode))) { 700 const A64EncodingMap *encoder = &EncodingMap[opcode]; 704 DCHECK(!opcode_is_wide || IS_WIDE(encoder->opcode)); 788 << "(" << UNWIDE(encoder->opcode) << ", " << encode 944 int16_t opcode = lir->opcode; local 1102 A64Opcode opcode = UNWIDE(lir->opcode); local 1113 A64Opcode opcode = UNWIDE(lir->opcode); local [all...] |
H A D | fp_arm64.cc | 26 void Arm64Mir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, argument 31 switch (opcode) { 59 LOG(FATAL) << "Unexpected opcode: " << opcode; 68 void Arm64Mir2Lir::GenArithOpDouble(Instruction::Code opcode, argument 73 switch (opcode) { 107 LOG(FATAL) << "Unexpected opcode: " << opcode; 147 void Arm64Mir2Lir::GenConversion(Instruction::Code opcode, argument 154 switch (opcode) { 279 GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument [all...] |
/art/compiler/dex/quick/ |
H A D | mir_to_lir-inl.h | 46 inline LIR* Mir2Lir::RawLIR(DexOffset dalvik_offset, int opcode, int op0, argument 50 insn->opcode = opcode; 58 if ((opcode == kPseudoTargetLabel) || (opcode == kPseudoSafepointPC) || 59 (opcode == kPseudoExportedPC)) { 71 inline LIR* Mir2Lir::NewLIR0(int opcode) { argument 72 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & NO_OPERAND)) 73 << GetTargetInstName(opcode) << " " << opcod 81 NewLIR1(int opcode, int dest) argument 91 NewLIR2(int opcode, int dest, int src1) argument 101 NewLIR2NoDest(int opcode, int src, int info) argument 111 NewLIR3(int opcode, int dest, int src1, int src2) argument 121 NewLIR4(int opcode, int dest, int src1, int src2, int info) argument 131 NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2) argument 166 int opcode = lir->opcode; local [all...] |
H A D | quick_compiler.cc | 521 int opcode = mir->dalvikInsn.opcode; local 523 if (std::find(unsupport_list, unsupport_list + unsupport_list_size, opcode) 525 if (!MIR::DecodedInstruction::IsPseudoMirOp(opcode)) { 527 << mir->dalvikInsn.opcode; 529 VLOG(compiler) << "Unsupported extended MIR opcode : " 530 << MIRGraph::extended_mir_op_names_[opcode - kMirOpFirst]; 535 if (std::find(kInvokeOpcodes, kInvokeOpcodes + arraysize(kInvokeOpcodes), opcode) 694 /* Gathering opcode stats? */
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H A D | dex_file_method_inliner.cc | 122 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); 123 if (IsInvokeInstructionRange(invoke->dalvikInsn.opcode)) { 126 DCHECK_EQ(Instruction::FormatOf(invoke->dalvikInsn.opcode), Instruction::k35c); 133 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); 134 return IsInvokeInstructionRange(invoke->dalvikInsn.opcode) || 537 if (kIntrinsicIsStatic[intrinsic.opcode] != (info->type == kStatic)) { 541 switch (intrinsic.opcode) { 618 LOG(FATAL) << "Unexpected intrinsic opcode: " << intrinsic.opcode; 656 switch (method.opcode) { 870 Instruction::Code opcode = Instruction::MOVE_FROM16; local 908 Instruction::Code opcode = static_cast<Instruction::Code>(Instruction::IGET + data.op_variant); local 957 Instruction::Code opcode = static_cast<Instruction::Code>(Instruction::IPUT + data.op_variant); local [all...] |
/art/compiler/dwarf/ |
H A D | debug_line_opcode_writer.h | 30 // * Choose the most compact encoding of a given opcode. 155 // Compact address and line opcode. 174 int opcode = kOpcodeBase + (delta_line - kLineBase) + local 176 if (opcode > UINT8_MAX) { 179 opcode -= (kLineRange * const_advance); 180 if (opcode <= UINT8_MAX) { 185 // Still use the opcode to do line advance and copy. 186 opcode = kOpcodeBase + (delta_line - kLineBase); 189 DCHECK(kOpcodeBase <= opcode && opcode < [all...] |
/art/runtime/arch/x86/ |
H A D | fault_handler_x86.cc | 102 uint8_t opcode = *pc++; local 113 switch (opcode) { 134 opcode = *pc++; 143 if (x86_64 && opcode >= 0x40 && opcode <= 0x4f) { 144 opcode = *pc++; 147 if (opcode == 0x0f) { 148 // Two byte opcode 150 opcode = *pc++; 156 switch (opcode) { [all...] |
/art/runtime/quick/ |
H A D | inline_method_analyser.cc | 85 Instruction::Code opcode = instruction->Opcode(); local 87 switch (opcode) { 90 method->opcode = kInlineOpNop; 154 result->opcode = kInlineOpReturnArg; 191 result->opcode = kInlineOpNonWideConst; 202 Instruction::Code opcode = instruction->Opcode(); local 203 DCHECK(IsInstructionIGet(opcode)); 207 if (!(return_opcode == Instruction::RETURN_WIDE && opcode == Instruction::IGET_WIDE) && 208 !(return_opcode == Instruction::RETURN_OBJECT && opcode == Instruction::IGET_OBJECT) && 209 !(return_opcode == Instruction::RETURN && opcode ! 265 Instruction::Code opcode = instruction->Opcode(); local [all...] |
H A D | inline_method_analyser.h | 140 InlineMethodOpcode opcode; member in struct:art::InlineMethod 162 static constexpr bool IsInstructionIGet(Instruction::Code opcode) { argument 163 return Instruction::IGET <= opcode && opcode <= Instruction::IGET_SHORT; 166 static constexpr bool IsInstructionIPut(Instruction::Code opcode) { argument 167 return Instruction::IPUT <= opcode && opcode <= Instruction::IPUT_SHORT; 170 static constexpr uint16_t IGetVariant(Instruction::Code opcode) { argument 171 return opcode - Instruction::IGET; 174 static constexpr uint16_t IPutVariant(Instruction::Code opcode) { argument [all...] |