Searched defs:r_dest (Results 1 - 13 of 13) sorted by relevance

/art/compiler/dex/quick/
H A Dgen_loadstore.cc31 LIR* Mir2Lir::LoadConstant(RegStorage r_dest, int value) { argument
32 if (IsTemp(r_dest)) {
33 Clobber(r_dest);
34 MarkInUse(r_dest);
36 return LoadConstantNoClobber(r_dest, value);
44 void Mir2Lir::LoadValueDirect(RegLocation rl_src, RegStorage r_dest) { argument
47 OpRegCopy(r_dest, rl_src.reg);
51 LoadConstantNoClobber(r_dest, mir_graph_->ConstantValue(rl_src));
64 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, op_size, kNotVolatile); local
73 void Mir2Lir::LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest) { argument
84 LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest) argument
94 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, k64, kNotVolatile); local
103 LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest) argument
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H A Dmir_to_lir.h974 virtual LIR* LoadConstant(RegStorage r_dest, int value);
976 LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { argument
977 return LoadBaseDisp(r_base, displacement, r_dest, kWord, kNotVolatile);
980 LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { argument
981 return LoadBaseDisp(r_base, displacement, r_dest, k32, kNotVolatile);
984 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, argument
986 return LoadBaseDisp(r_base, displacement, r_dest, kReference, is_volatile);
989 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) { argument
990 return LoadBaseIndexed(r_base, r_index, r_dest, scale, kReference);
997 virtual void LoadValueDirect(RegLocation rl_src, RegStorage r_dest);
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/art/compiler/dex/quick/mips/
H A Dutility_mips.cc32 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { argument
35 DCHECK_EQ(r_dest.Is64Bit(), r_src.Is64Bit());
36 if (r_dest.Is64Bit()) {
37 if (r_dest.IsDouble()) {
43 r_src = r_dest;
44 r_dest = t_opnd;
52 if (r_dest.IsSingle()) {
58 r_src = r_dest;
59 r_dest = t_opnd;
69 DCHECK_EQ(r_dest
130 LoadConstantNoClobber(RegStorage r_dest, int value) argument
163 LoadConstantWideNoClobber(RegStorage r_dest, int64_t value) argument
304 OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) argument
346 OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) argument
523 OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) argument
536 OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) argument
542 LoadConstantWide(RegStorage r_dest, int64_t value) argument
569 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument
690 LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size) argument
851 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
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H A Dint_mips.cc181 LIR* MipsMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { argument
187 if (r_dest.IsPair()) {
188 r_dest = r_dest.GetLow();
194 DCHECK(!r_dest.IsPair() && !r_src.IsPair());
197 if (r_dest.IsFloat() || r_src.IsFloat())
198 return OpFpRegCopy(r_dest, r_src);
200 // TODO: Check that r_src and r_dest are both 32 or both 64 bits length on Mips64.
201 if (r_dest.Is64Bit() || r_src.Is64Bit()) {
209 res = RawLIR(current_dalvik_offset_, opcode, r_dest
216 OpRegCopy(RegStorage r_dest, RegStorage r_src) argument
223 OpRegCopyWide(RegStorage r_dest, RegStorage r_src) argument
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H A Dtarget_mips.cc789 LIR* MipsMir2Lir::GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest) { argument
790 DCHECK(!r_dest.IsFloat()); // See RegClassForFieldLoadStore().
792 DCHECK(r_dest.IsPair());
803 OpRegCopy(r_dest, TargetReg(kRet0));
806 OpRegCopyWide(r_dest, reg_ret);
/art/compiler/dex/quick/x86/
H A Dfp_x86.cc65 RegStorage r_dest = rl_result.reg; local
68 if (r_dest == r_src2) {
70 OpRegCopy(r_src2, r_dest);
72 OpRegCopy(r_dest, r_src1);
73 NewLIR2(op, r_dest.GetReg(), r_src2.GetReg());
H A Dutility_x86.cc33 LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { argument
36 DCHECK(r_dest.IsFloat() || r_src.IsFloat());
37 DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble());
38 if (r_dest.IsDouble()) {
41 if (r_dest.IsSingle()) {
53 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
54 if (r_dest == r_src) {
84 * 1) r_dest is freshly returned from AllocTemp or
87 LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { argument
88 RegStorage r_dest_save = r_dest;
257 OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) argument
362 OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) argument
370 OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) argument
426 OpRegMem(OpKind op, RegStorage r_dest, RegLocation rl_value) argument
451 OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) argument
504 OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int value) argument
567 LoadConstantWide(RegStorage r_dest, int64_t value) argument
643 LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_dest, OpSize size) argument
771 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument
776 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
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H A Dint_x86.cc126 LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { argument
128 if (r_dest.IsPair()) {
129 r_dest = r_dest.GetLow();
134 if (r_dest.IsFloat() || r_src.IsFloat())
135 return OpFpRegCopy(r_dest, r_src);
136 LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR,
137 r_dest.GetReg(), r_src.GetReg());
138 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
144 void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorag argument
151 OpRegCopyWide(RegStorage r_dest, RegStorage r_src) argument
1400 OpLoadPc(RegStorage r_dest) argument
1428 OpPcRelDexCacheArrayLoad(const DexFile* dex_file, int offset, RegStorage r_dest, bool wide) argument
2406 OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) argument
2419 OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset) argument
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H A Dtarget_x86.cc767 RegStorage r_dest = cu_->target64 ? RegStorage::Solo64(reg) : RegStorage::Solo32(reg); local
768 LoadBaseDisp(rs_rSP, offset, r_dest, size, kNotVolatile);
/art/compiler/dex/quick/arm/
H A Dutility_arm.cc77 LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) { argument
78 DCHECK(RegStorage::IsSingle(r_dest));
83 NewLIR2(kThumb2Vmovs_IMM8, r_dest, 0);
85 return NewLIR3(kThumb2Vsubs, r_dest, r_dest, r_dest);
89 return NewLIR2(kThumb2Vmovs_IMM8, r_dest, encoded_imm);
98 r_dest, rs_r15pc.GetReg(), 0, 0, 0, data_target);
220 * 1) r_dest is freshly returned from AllocTemp or
223 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, in argument
422 OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) argument
434 OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) argument
440 OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, int shift) argument
509 OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) argument
513 OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) argument
697 LoadConstantWide(RegStorage r_dest, int64_t value) argument
748 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument
910 LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size) argument
1030 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
1226 OpFpRegCopy(RegStorage r_dest, RegStorage r_src) argument
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H A Dint_arm.cc414 LIR* ArmMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { argument
418 if (r_dest.IsPair()) {
419 r_dest = r_dest.GetLow();
424 if (r_dest.IsFloat() || r_src.IsFloat())
425 return OpFpRegCopy(r_dest, r_src);
426 if (r_dest.Low8() && r_src.Low8())
428 else if (!r_dest.Low8() && !r_src.Low8())
430 else if (r_dest.Low8())
434 res = RawLIR(current_dalvik_offset_, opcode, r_dest
441 OpRegCopy(RegStorage r_dest, RegStorage r_src) argument
448 OpRegCopyWide(RegStorage r_dest, RegStorage r_src) argument
654 GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops) argument
1099 OpPcRelDexCacheArrayAddr(const DexFile* dex_file, int offset, RegStorage r_dest) argument
1115 OpPcRelDexCacheArrayLoad(const DexFile* dex_file, int offset, RegStorage r_dest, bool wide) argument
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/art/compiler/dex/quick/arm64/
H A Dutility_arm64.cc112 LIR* Arm64Mir2Lir::LoadFPConstantValue(RegStorage r_dest, int32_t value) { argument
113 DCHECK(r_dest.IsSingle());
115 return NewLIR2(kA64Fmov2sw, r_dest.GetReg(), rwzr);
119 return NewLIR2(kA64Fmov2fI, r_dest.GetReg(), encoded_imm);
131 r_dest.GetReg(), 0, 0, 0, 0, data_target);
136 LIR* Arm64Mir2Lir::LoadFPConstantValueWide(RegStorage r_dest, int64_t value) { argument
137 DCHECK(r_dest.IsDouble());
139 return NewLIR2(kA64Fmov2Sx, r_dest.GetReg(), rxzr);
143 return NewLIR2(WIDE(kA64Fmov2fI), r_dest.GetReg(), encoded_imm);
157 r_dest
394 LoadConstantNoClobber(RegStorage r_dest, int value) argument
458 LoadConstantWide(RegStorage r_dest, int64_t value) argument
675 OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) argument
689 OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) argument
695 OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, int shift) argument
763 OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, A64RegExtEncodings ext, uint8_t amount) argument
801 OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) argument
805 OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) argument
809 OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value) argument
1024 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument
1191 LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size) argument
1272 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument
1384 OpFpRegCopy(RegStorage r_dest, RegStorage r_src) argument
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H A Dint_arm64.cc314 LIR* Arm64Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { argument
315 bool dest_is_fp = r_dest.IsFloat();
322 DCHECK_EQ(r_dest.Is64Bit(), r_src.Is64Bit());
326 opcode = UNLIKELY(A64_REG_IS_SP(r_dest.GetReg())) ? kA64Add4RRdT : kA64Mov2rr;
333 if (r_dest.Is64Bit() && r_src.Is64Bit()) {
338 bool dest_is_double = r_dest.IsDouble();
350 if (r_dest.IsDouble()) {
360 r_dest = Check32BitReg(r_dest);
366 res = RawLIR(current_dalvik_offset_, opcode, r_dest
375 OpRegCopy(RegStorage r_dest, RegStorage r_src) argument
382 OpRegCopyWide(RegStorage r_dest, RegStorage r_src) argument
950 OpPcRelDexCacheArrayLoad(const DexFile* dex_file, int offset, RegStorage r_dest, bool wide) argument
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