Searched defs:szB (Results 26 - 41 of 41) sorted by relevance

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/external/valgrind/none/tests/amd64/
H A Dsse4-64.c28 static void* memalign16(size_t szB) argument
33 x = malloc(szB);
35 x = memalign(16, szB);
/external/valgrind/VEX/priv/
H A Dhost_amd64_defs.h512 UChar szB; /* 4 or 8 only */ member in struct:__anon15061::__anon15062::__anon15079
520 UChar szB; /* 4 or 8 only */ member in struct:__anon15061::__anon15062::__anon15080
584 UChar szB; /* 4 or 8 */ member in struct:__anon15061::__anon15062::__anon15090
729 extern AMD64Instr* AMD64Instr_CLoad ( AMD64CondCode cond, UChar szB,
731 extern AMD64Instr* AMD64Instr_CStore ( AMD64CondCode cond, UChar szB,
744 extern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB );
H A Dhost_arm64_defs.c221 ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB ) {
226 am->ARM64am.RI12.szB = szB;
228 switch (szB) {
251 vex_printf("%u(", (UInt)am->ARM64am.RI12.szB
994 ARM64Instr* ARM64Instr_LdrEX ( Int szB ) {
997 i->ARM64in.LdrEX.szB = szB;
998 vassert(szB == 8 || szB
1327 ARM64Instr_VMov( UInt szB, HReg dst, HReg src ) argument
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H A Dhost_arm_defs.h752 Int szB; /* 1, 2, 4 or 8 */ member in struct:__anon15250::__anon15251::__anon15268
760 Int szB; /* 1, 2, 4 or 8 */ member in struct:__anon15250::__anon15251::__anon15269
985 extern ARMInstr* ARMInstr_LdrEX ( Int szB );
986 extern ARMInstr* ARMInstr_StrEX ( Int szB );
H A Dhost_arm64_defs.h119 ARM64am_RI12, /* reg + uimm12 * szB (iow, scaled by access size) */
135 UChar szB; /* 1, 2, 4, 8 (16 ?) */ member in struct:__anon15114::__anon15115::__anon15117
146 extern ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB );
664 Int szB; /* 1, 2, 4 or 8 */ member in struct:__anon15147::__anon15148::__anon15169
668 Int szB; /* 1, 2, 4 or 8 */ member in struct:__anon15147::__anon15148::__anon15170
865 UInt szB; // 16=mov qD,qS; 8=mov dD,dS; 4=mov sD,sS member in struct:__anon15147::__anon15148::__anon15202
909 extern ARM64Instr* ARM64Instr_LdrEX ( Int szB );
910 extern ARM64Instr* ARM64Instr_StrEX ( Int szB );
950 extern ARM64Instr* ARM64Instr_VMov ( UInt szB, HReg dst, HReg src );
H A Dguest_amd64_toIR.c2281 Int szB = vbi->guest_stack_redzone_size; local
2282 vassert(szB >= 0);
2287 vassert(szB == 128);
2292 if (szB > 0)
2294 binop(Iop_Sub64, mkexpr(new_rsp), mkU64(szB)),
2295 szB,
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H A Dguest_arm64_toIR.c1396 static IRType preferredVectorSubTypeFromSize ( UInt szB )
1398 switch (szB) {
4572 static void gen_narrowing_store ( UInt szB, IRTemp addr, IRExpr* dataE ) argument
4575 switch (szB) {
4596 static IRTemp gen_zwidening_load ( UInt szB, IRTemp addr ) argument
4600 switch (szB) {
4658 UInt szB = 1 << szLg2; local
4660 UInt offs = INSN(21,10) * szB;
4668 putIReg64orZR(tt, mkexpr(gen_zwidening_load(szB, ta)));
4670 gen_narrowing_store(szB, t
4709 UInt szB = 1 << szLg2; local
5028 UInt szB = 1 << szLg2; local
5262 UInt szB = 4 << szSlg2; /* szB is the per-register size */ local
5629 UInt szB = 4 << INSN(31,30); local
6321 UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */ local
6373 UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */ local
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H A Dguest_ppc_toIR.c1770 Int szB = vbi->guest_stack_redzone_size; local
1772 vassert(szB >= 0);
1773 if (szB > 0) {
1777 binop(Iop_Sub64, getIReg(1), mkU64(szB)),
1778 szB,
1784 binop(Iop_Sub32, getIReg(1), mkU32(szB)),
1785 szB,
/external/valgrind/exp-sgcheck/
H A Dsg_main.c174 if (fb1->szB < fb2->szB) return -1;
175 if (fb1->szB > fb2->szB) return 1;
187 /* Returns True if all fields except .szB are the same. szBs may or
229 " StackBlock{ off %ld szB %lu spRel:%c isVec:%c \"%s\" }\n",
230 sb->base, sb->szB, sb->spRel ? 'Y' : 'N',
299 /* StackBlock{ off 16 szB 66 spRel:Y isVec:Y "sz" }
300 StackBlock{ off 16 szB 130 spRel:Y isVec:Y "sz" }
301 StackBlock{ off 208 szB 1
473 SizeT szB; /* copied from .descr->szB */ member in struct:__anon16285
627 SizeT szB; /* copied from .descr->szB */ member in struct:__anon16286
823 SizeT szB; member in struct:__anon16288::__anon16289::__anon16292
902 SizeT szB = 0; local
1001 SizeT szB; member in struct:__anon16295
1516 classify_address( Invar* inv, ThreadId tid, Addr ea, Addr sp, Addr fp, UWord szB, XArray* thisInstrBlocks ) argument
1776 UWord szB; local
2125 instrument_mem_access( struct _SGEnv* sge, IRSB* bbOut, IRExpr* addr, Int szB, Bool isStore, Int hWordTy_szB, Addr curr_IP, const VexGuestLayout* layout ) argument
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/external/valgrind/massif/
H A Dms_main.c535 SizeT szB; member in struct:_XPt
558 SizeT szB; // memory size for the node, be it Sig or Insig member in struct:_SXPt
589 xpt->szB = 0;
633 return ( sxpt1->szB < sxpt2->szB ? 1
634 : sxpt1->szB > sxpt2->szB ? -1
673 if (xpt->children[i]->szB >= sig_child_threshold_szB) {
684 sxpt->szB = xpt->szB;
1974 SizeT szB = argv[2]; local
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/external/valgrind/coregrind/m_debuginfo/
H A Dreaddwarf3.c209 return c->sli_next >= c->sli.ioff + c->sli.szB;
227 return c->sli.ioff + c->sli.szB - c->sli_next;
244 if (c->sli_next + sizeof(UChar) > c->sli.ioff + c->sli.szB) {
256 if (c->sli_next + sizeof(UShort) > c->sli.ioff + c->sli.szB) {
268 if (c->sli_next + sizeof(UInt) > c->sli.ioff + c->sli.szB) {
280 if (c->sli_next + sizeof(ULong) > c->sli.ioff + c->sli.szB) {
528 /* The use of escn_debug_{info,types}.szB seems safe to me even if
530 sections were not found), because DiSlice_INVALID.szB is always
533 if (die >= cc->escn_debug_info.szB) {
534 if (die >= cc->escn_debug_info.szB
1124 Long szB; // 1, 2, 4, 8 or non-positive values only. member in struct:__anon15934
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H A Dreadpdb.c2536 Int szB = (Int)stat_buf.size; local
2537 if (szB == 0) {
2542 if (szB < 6 || szB > 1024/*let's say*/) {
2544 tmpname, szB);
2548 HChar* pdbname = ML_(dinfo_zalloc)("di.readpe.fnopf.pdbname", szB + 1);
2549 pdbname[szB] = 0;
2551 Int nread = VG_(read)(fd, pdbname, szB);
2552 if (nread != szB) {
2556 vg_assert(pdbname[szB]
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/external/valgrind/helgrind/
H A Dhg_main.c3985 SizeT szB; /* size requested */ member in struct:__anon16321
4013 SizeT szB, SizeT alignB, Bool is_zeroed )
4018 tl_assert( ((SSizeT)szB) >= 0 );
4019 p = (Addr)VG_(cli_malloc)(alignB, szB);
4024 VG_(memset)((void*)p, 0, szB);
4031 md->szB = szB;
4038 evh__new_mem_heap( p, szB, is_zeroed );
4081 SizeT szB; local
4089 szB
4012 handle_alloc( ThreadId tid, SizeT szB, SizeT alignB, Bool is_zeroed ) argument
4219 mm_find_containing_block( ExeContext** where, UInt* tnr, Addr* payload, SizeT* szB, Addr data_addr ) argument
4295 instrument_mem_access( IRSB* sbOut, IRExpr* addr, Int szB, Bool isStore, Int hWordTy_szB, Int goff_sp, IRExpr* guard ) argument
4864 SizeT szB = 1; local
[all...]
H A Dlibhb_core.c425 /* True if a belongs in range [start, start + szB[
426 (i.e. start + szB is excluded). */
427 static inline Bool address_in_range (Addr a, Addr start, SizeT szB) argument
429 /* Checking start <= a && a < start + szB.
433 tl_assert ((a - start < szB)
435 && a < start + szB));
436 return a - start < szB;
1648 static void shmem__invalidate_scache_range (Addr ga, SizeT szB) argument
1654 /* szB must be a multiple of cacheline size. */
1655 tl_assert (0 == (szB
4445 UInt szB : 32 - SCALARTS_N_THRBITS - 1; member in struct:__anon16342
4582 event_map_bind( Addr a, SizeT szB, Bool isW, Thr* thr ) argument
4652 libhb_event_map_lookup( ExeContext** resEC, Thr** resThr, SizeT* resSzB, Bool* resIsW, WordSetID* locksHeldW, Thr* thr, Addr a, SizeT szB, Bool isW ) argument
4759 libhb_event_map_access_history( Addr a, SizeT szB, Access_t fn ) argument
4978 record_race_info( Thr* acc_thr, Addr acc_addr, SizeT szB, Bool isWrite, VtsID Cfailed, VtsID Kfailed, VtsID Cw ) argument
6732 TRACEME(Addr a, SizeT szB) argument
6737 trace( Thr* thr, Addr a, SizeT szB, const HChar* s ) argument
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/external/valgrind/memcheck/
H A Dmc_main.c1200 SSizeT szB = nBits / 8; local
1201 SSizeT szL = szB / 8; /* Size in Longs (64-bit units) */
1210 tl_assert((szB & (szB-1)) == 0 && szL > 0);
1255 MC_(record_address_error)( VG_(get_running_tid)(), a, szB, False );
1288 if (0 == (a & (szB - 1)) && n_addrs_bad < szB) {
1304 MC_(record_address_error)( VG_(get_running_tid)(), a, szB, False );
1348 SSizeT szB = nBits / 8; local
1365 for (i = szB
1458 SizeT szB = nBits / 8; local
4933 mc_get_or_set_vbits_for_client( Addr a, Addr vbits, SizeT szB, Bool setting, Bool is_client_request ) argument
5550 SizeT szB = 1; local
5687 SizeT szB = 1; local
5708 SizeT szB = 1; local
5793 SizeT szB = 1; local
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H A Dmc_translate.c1333 VG_(tool_panic)("unexpected szB");
5532 static IRAtom* gen_load_b ( MCEnv* mce, Int szB,
5535 static void gen_store_b ( MCEnv* mce, Int szB,
6740 static IRAtom* gen_guarded_load_b ( MCEnv* mce, Int szB, argument
6758 switch (szB) {
6778 VG_(printf)("mc_translate.c: gen_load_b: unhandled szB == %d\n", szB);
6813 static IRAtom* gen_load_b ( MCEnv* mce, Int szB, IRAtom* baseaddr, argument
6816 return gen_guarded_load_b(mce, szB, baseaddr, offset, NULL/*guard*/);
6856 static void gen_store_b ( MCEnv* mce, Int szB, argument
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