Searched refs:Register (Results 26 - 50 of 55) sorted by relevance

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/art/compiler/utils/arm/
H A Dassembler_arm32_test.cc44 arm::Register, arm::SRegister,
69 new arm::Register(arm::R0),
70 new arm::Register(arm::R1),
71 new arm::Register(arm::R4),
72 new arm::Register(arm::R8),
73 new arm::Register(arm::R11),
74 new arm::Register(arm::R12),
75 new arm::Register(arm::R13),
76 new arm::Register(arm::R14),
77 new arm::Register(ar
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H A Dconstants_arm.h270 Register RnField() const { return static_cast<Register>(
272 Register RdField() const { return static_cast<Register>(
281 Register RmField() const {
282 return static_cast<Register>(Bits(kRmShift, kRmBits));
287 Register RsField() const {
288 return static_cast<Register>(Bits(kRsShift, kRsBits));
H A Dmanaged_register_arm.cc29 Register low = AsRegisterPairLow();
30 Register high = AsRegisterPairHigh();
60 low = (r - kNumberOfDRegIds) * 2; // Return a Register.
77 os << "No Register";
H A Dmanaged_register_arm.h58 // Register ids map:
59 // [0..R[ core registers (enum Register)
70 // [0..R[ core registers (enum Register)
82 // core register (enum Register), a VFP single precision register
88 Register AsCoreRegister() const {
90 return static_cast<Register>(id_);
117 Register reg_low = AsRegisterPairLow();
125 Register AsRegisterPairLow() const {
131 Register AsRegisterPairHigh() const {
185 static ArmManagedRegister FromCoreRegister(Register
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H A Dassembler_arm.cc38 std::ostream& operator<<(std::ostream& os, const Register& rhs) {
42 os << "Register[" << static_cast<int>(rhs) << "]";
114 // Register shift.
219 // Register offset, possibly shifted.
373 static dwarf::Reg DWARFReg(Register reg) {
402 cfi_.RelOffsetForMany(DWARFReg(Register(0)), 0, core_spill_mask, kFramePointerSize);
573 Register src_register, int32_t src_offset, size_t size) {
695 Register scratch = mscratch.AsArm().AsCoreRegister();
703 Register scratch = mscratch.AsArm().AsCoreRegister();
718 Register scratc
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/art/compiler/utils/x86/
H A Dmanaged_register_x86.cc42 Register low;
43 Register high;
68 Register low = AsRegisterPairLow();
69 Register high = AsRegisterPairHigh();
100 os << "No Register";
H A Dmanaged_register_x86.h64 // Register ids map:
65 // [0..R[ cpu registers (enum Register)
76 // [0..R[ cpu registers (enum Register)
86 // Register), an xmm register (enum XmmRegister), or a pair of cpu registers
98 Register AsCpuRegister() const {
100 return static_cast<Register>(id_);
114 Register AsRegisterPairLow() const {
120 Register AsRegisterPairHigh() const {
163 static X86ManagedRegister FromCpuRegister(Register r) {
/art/compiler/utils/x86_64/
H A Dmanaged_register_x86_64.cc41 Register low;
42 Register high;
63 Register low = AsRegisterPairLow().AsRegister();
64 Register high = AsRegisterPairHigh().AsRegister();
95 os << "No Register";
H A Dmanaged_register_x86_64.h63 // Register ids map:
64 // [0..R[ cpu registers (enum Register)
75 // [0..R[ cpu registers (enum Register)
85 // Register), an xmm register (enum XmmRegister), or a pair of cpu registers
93 return CpuRegister(static_cast<Register>(id_));
150 static X86_64ManagedRegister FromCpuRegister(Register r) {
H A Dassembler_x86_64.cc268 EmitOperand(Register::RAX, dst);
329 EmitOperand(Register::RAX, dst);
1492 void X86_64Assembler::rex(bool force, bool w, Register* r, Register* x, Register* b) {
1502 if (r != nullptr && *r >= Register::R8 && *r < Register::kNumberOfCpuRegisters) {
1504 *r = static_cast<Register>(*r - 8);
1506 if (x != nullptr && *x >= Register::R8 && *x < Register
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H A Dassembler_x86_64.h63 Register rm() const {
64 return static_cast<Register>(encoding_at(0) & 7);
71 Register index() const {
72 return static_cast<Register>((encoding_at(1) >> 3) & 7);
75 Register base() const {
76 return static_cast<Register>(encoding_at(1) & 7);
97 && ((encoding_[0] & 0x07) == reg.LowBits()) // Register codes match.
/art/runtime/arch/arm/
H A Dregisters_arm.h26 enum Register { enum in namespace:art::arm
52 std::ostream& operator<<(std::ostream& os, const Register& rhs);
/art/runtime/arch/mips/
H A Dregisters_mips.h29 enum Register { enum in namespace:art::mips
65 std::ostream& operator<<(std::ostream& os, const Register& rhs);
/art/compiler/utils/mips/
H A Dmanaged_register_mips.h64 // Register ids map:
65 // [0..R[ core registers (enum Register)
76 // [0..R[ core registers (enum Register)
84 // Register), a single precision FP register (enum FRegister), a double precision
90 Register AsCoreRegister() const {
92 return static_cast<Register>(id_);
117 Register AsRegisterPairLow() const {
123 Register AsRegisterPairHigh() const {
167 static MipsManagedRegister FromCoreRegister(Register r) {
H A Dmanaged_register_mips.cc30 Register low = AsRegisterPairLow();
31 Register high = AsRegisterPairHigh();
61 low = (r - kNumberOfDRegIds) * 2 + 2; // Return a Register.
78 os << "No Register";
/art/compiler/optimizing/
H A Dcode_generator_arm64.h38 static const vixl::Register kParameterCoreRegisters[] = {
47 const vixl::Register tr = vixl::x18; // Thread Register
48 static const vixl::Register kArtMethodRegister = vixl::x0; // Method register on invoke.
80 static const vixl::Register kRuntimeParameterCoreRegisters[] =
89 class InvokeRuntimeCallingConvention : public CallingConvention<vixl::Register, vixl::FPRegister> {
106 class InvokeDexCallingConvention : public CallingConvention<vixl::Register, vixl::FPRegister> {
155 void GenerateClassInitializationCheck(SlowPathCodeARM64* slow_path, vixl::Register class_reg);
271 void MarkGCCard(vixl::Register object, vixl::Register valu
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H A Dcode_generator_arm64.cc490 Register temp = temps.AcquireX();
551 Register dst = RegisterFrom(location, type);
558 Register temp = (instruction->IsIntConstant() || instruction->IsNullConstant())
606 void CodeGeneratorARM64::MarkGCCard(Register object, Register value) {
608 Register card = temps.AcquireX();
609 Register temp = temps.AcquireW(); // Index within the CardTable - 32bit.
669 Register reg = Register(VIXLRegCodeFromART(reg_id), kXRegSize);
675 Register re
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H A Dintrinsics_arm64.cc79 Register trg_reg = RegisterFrom(trg, type);
80 Register res_reg = RegisterFrom(ARM64ReturnLocation(type), type);
335 Register in_reg = is64bit ? XRegisterFrom(in) : WRegisterFrom(in);
336 Register out_reg = is64bit ? XRegisterFrom(output) : WRegisterFrom(output);
425 Register op1_reg = is_long ? XRegisterFrom(op1) : WRegisterFrom(op1);
426 Register op2_reg = is_long ? XRegisterFrom(op2) : WRegisterFrom(op2);
427 Register out_reg = is_long ? XRegisterFrom(out) : WRegisterFrom(out);
527 Register out_reg = is_double ?
667 Register base = WRegisterFrom(locations->InAt(1)); // Object pointer.
668 Register offse
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H A Dcode_generator_x86_64.h33 static constexpr Register kParameterCoreRegisters[] = { RSI, RDX, RCX, R8, R9 };
40 static constexpr Register kRuntimeParameterCoreRegisters[] = { RDI, RSI, RDX, RCX };
47 class InvokeRuntimeCallingConvention : public CallingConvention<Register, FloatRegister> {
60 class InvokeDexCallingConvention : public CallingConvention<Register, FloatRegister> {
/art/compiler/utils/arm64/
H A Dassembler_arm64.h185 static vixl::Register reg_x(int code) {
192 return vixl::Register::XRegFromCode(code);
195 static vixl::Register reg_w(int code) {
202 return vixl::Register::WRegFromCode(code);
251 // Register used for passing Thread::Current()->exception_ .
H A Dassembler_arm64.cc89 vixl::Register temp = temps.AcquireX();
184 vixl::Register temp = temps.AcquireX();
209 vixl::Register temp = temps.AcquireX();
621 vixl::Register temp = temps.AcquireX();
654 const Register sp = vixl_masm_->StackPointer();
673 const Register sp = vixl_masm_->StackPointer();
/art/compiler/jni/quick/arm/
H A Dcalling_convention_arm.cc26 static const Register kHFCoreArgumentRegisters[] = {
295 static const Register kJniArgumentRegisters[] = {
/art/compiler/jni/quick/mips/
H A Dcalling_convention_mips.cc186 static const Register kJniArgumentRegisters[] = {
/art/runtime/
H A Dthread_list.h136 void Register(Thread* self)
/art/compiler/dwarf/
H A Ddebug_frame_opcode_writer.h166 void ALWAYS_INLINE Register(Reg reg, Reg new_reg) { function in class:art::dwarf::DebugFrameOpCodeWriter

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