| /external/llvm/lib/CodeGen/ |
| H A D | RegAllocGreedy.cpp | 1658 const LiveRange &LR = LIS->getRegUnit(*Units); local
1659 LiveRange::const_iterator I = LR.find(StartIdx);
1660 LiveRange::const_iterator E = LR.end();
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandPseudoInsts.cpp | 704 .addReg(AArch64::LR);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 49 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {}
84 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
527 // R7, LR
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| H A D | Thumb2SizeReduction.cpp | 350 if (isLROk && Reg == ARM::LR)
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| H A D | ARMExpandPseudoInsts.cpp | 1075 .addReg(ARM::LR)
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| H A D | ARMLoadStoreOptimizer.cpp | 1778 /// directly restore the value of LR into pc.
1802 if (MO.getReg() != ARM::LR)
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| H A D | RegionStore.cpp | 1028 if (const MemRegion *LR = L->getAsRegion())
1029 AddToWorkList(LR);
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 3001 .Case("r14", ARM::LR)
3377 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3378 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
5968 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5975 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
6030 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6038 "PC and LR may not be in the register list simultaneously");
6114 if (RtReg == ARM::LR)
6350 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
8279 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBas
[all...] |
| /external/cblas/testing/ |
| H A D | c_zblat2.f | 2589 LOGICAL FUNCTION LZE( RI, RJ, LR )
2600 INTEGER LR local in function:LZE
2606 DO 10 I = 1, LR
|
| /external/eigen/blas/testing/ |
| H A D | cblat2.f | 3002 LOGICAL FUNCTION LCE( RI, RJ, LR )
3013 INTEGER LR local in function:LCE
3019 DO 10 I = 1, LR
|
| H A D | cblat3.f | 707 DATA ICHS/'LR'/, ICHU/'UL'/
987 DATA ICHU/'UL'/, ICHT/'NTC'/, ICHD/'UN'/, ICHS/'LR'/
3187 LOGICAL FUNCTION LCE( RI, RJ, LR )
3200 INTEGER LR local in function:LCE
3206 DO 10 I = 1, LR
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| H A D | dblat2.f | 2905 LOGICAL FUNCTION LDE( RI, RJ, LR )
2916 INTEGER LR local in function:LDE
2922 DO 10 I = 1, LR
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| H A D | dblat3.f | 689 DATA ICHS/'LR'/, ICHU/'UL'/
960 DATA ICHU/'UL'/, ICHT/'NTC'/, ICHD/'UN'/, ICHS/'LR'/
2579 LOGICAL FUNCTION LDE( RI, RJ, LR )
2592 INTEGER LR local in function:LDE
2598 DO 10 I = 1, LR
|
| H A D | sblat2.f | 2905 LOGICAL FUNCTION LSE( RI, RJ, LR )
2916 INTEGER LR local in function:LSE
2922 DO 10 I = 1, LR
|
| H A D | sblat3.f | 689 DATA ICHS/'LR'/, ICHU/'UL'/
960 DATA ICHU/'UL'/, ICHT/'NTC'/, ICHD/'UN'/, ICHS/'LR'/
2579 LOGICAL FUNCTION LSE( RI, RJ, LR )
2592 INTEGER LR local in function:LSE
2598 DO 10 I = 1, LR
|
| H A D | zblat2.f | 3010 LOGICAL FUNCTION LZE( RI, RJ, LR )
3021 INTEGER LR local in function:LZE
3027 DO 10 I = 1, LR
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| H A D | zblat3.f | 708 DATA ICHS/'LR'/, ICHU/'UL'/
989 DATA ICHU/'UL'/, ICHT/'NTC'/, ICHD/'UN'/, ICHS/'LR'/
3193 LOGICAL FUNCTION LZE( RI, RJ, LR )
3206 INTEGER LR local in function:LZE
3212 DO 10 I = 1, LR
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| /external/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 1393 Value *LR = LU->getOperand(1); local
1396 L = LR;
1397 else if (LR == I)
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| /external/valgrind/memcheck/ |
| H A D | mc_machine.c | 179 if (o == GOF(LR) && sz == 8) return o;
378 if (o == GOF(LR) && sz == 4) return o;
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 367 AArch64::LR, AArch64::XZR
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 1169 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
|
| /external/lldb/source/Plugins/Instruction/ARM/ |
| H A D | EmulateInstructionARM.cpp | 371 // The M bit represents LR.
773 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
870 // if Rd == �1111� && S == �1� then SEE SUBS PC, LR and related instructions;
1078 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1432 LR = PC - 4;
1434 LR = PC<31:1> : '1';
1530 LR = next_instr_addr;
1533 LR = next_instr_addr<31:1> : '1';
1851 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
5661 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR an
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1872 .Case("lr", AArch64::LR)
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 888 ARM::R12, ARM::SP, ARM::LR, ARM::PC
|
| /external/clang/lib/Sema/ |
| H A D | SemaDeclCXX.cpp | 13540 } else if (const auto *LR = dyn_cast<LockReturnedAttr>(A))
13541 Arg = LR->getArg();
|