/external/mesa3d/src/gallium/drivers/nv30/ |
H A D | nv30_transfer.h | 5 struct nouveau_bo *bo; member in struct:nv30_rect
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | radeonsi_shader.h | 76 struct si_resource *bo; member in struct:si_pipe_shader
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H A D | radeonsi_pm4.h | 55 struct si_resource *bo[SI_PM4_MAX_BO]; member in struct:si_pm4_state 69 struct si_resource *bo,
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/external/libdrm/tests/planetest/ |
H A D | modeset.c | 10 #include "bo.h" 161 if (plane->bo) { 162 free_sp_bo(plane->bo); 163 plane->bo = NULL; 174 w = plane->bo->width; 175 h = plane->bo->height; 183 crtc->crtc->crtc_id, plane->bo->fb_id, 0, x, y, w, h, 198 w = plane->bo->width; 199 h = plane->bo->height; 209 plane->fb_pid, plane->bo [all...] |
/external/mesa3d/src/gallium/drivers/nv50/ |
H A D | nv50_transfer.c | 24 rect->bo = mt->base.bo; 69 nouveau_bufctx_refn(bctx, 0, src->bo, src->domain | NOUVEAU_BO_RD); 70 nouveau_bufctx_refn(bctx, 0, dst->bo, dst->domain | NOUVEAU_BO_WR); 74 if (nouveau_bo_memtype(src->bo)) { 91 if (nouveau_bo_memtype(dst->bo)) { 112 PUSH_DATAh(push, src->bo->offset + src_ofst); 113 PUSH_DATAh(push, dst->bo->offset + dst_ofst); 116 PUSH_DATA (push, src->bo->offset + src_ofst); 117 PUSH_DATA (push, dst->bo 384 nv50_cb_push(struct nouveau_context *nv, struct nouveau_bo *bo, unsigned domain, unsigned base, unsigned size, unsigned offset, unsigned words, const uint32_t *data) argument [all...] |
/external/mesa3d/src/mesa/drivers/dri/i915/ |
H A D | intel_regions.c | 127 if (drm_intel_bo_busy(region->bo)) { 137 drm_intel_gem_bo_map_gtt(region->bo); 139 drm_intel_bo_map(region->bo, true); 141 region->map = region->bo->virtual; 157 drm_intel_gem_bo_unmap_gtt(region->bo); 159 drm_intel_bo_unmap(region->bo); 184 region->bo = buffer; 226 if (drm_intel_bo_flink(region->bo, ®ion->name)) 321 drm_intel_bo_unreference(region->bo); 394 src_pitch, src->bo, src_offse [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | intel_regions.c | 127 if (drm_intel_bo_busy(region->bo)) { 137 drm_intel_gem_bo_map_gtt(region->bo); 139 drm_intel_bo_map(region->bo, true); 141 region->map = region->bo->virtual; 157 drm_intel_gem_bo_unmap_gtt(region->bo); 159 drm_intel_bo_unmap(region->bo); 184 region->bo = buffer; 226 if (drm_intel_bo_flink(region->bo, ®ion->name)) 321 drm_intel_bo_unreference(region->bo); 394 src_pitch, src->bo, src_offse [all...] |
H A D | gen7_wm_surface_state.c | 127 assert ((mcs_mt->region->bo->offset & 0xfff) == 0); 130 surf->ss6.mcs_enabled.mcs_base_address = mcs_mt->region->bo->offset >> 12; 131 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 134 mcs_mt->region->bo, 242 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL; local 260 if (bo) { 261 surf->ss1.base_addr = bo->offset; /* reloc */ 267 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 270 bo, 0, 352 intelObj->mt->region->bo 404 gen7_create_constant_surface(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, int width, uint32_t *out_offset) argument [all...] |
H A D | brw_state_dump.c | 43 uint32_t *data = intel->batch.bo->virtual + offset; 84 struct brw_vs_unit_state *vs = intel->batch.bo->virtual + offset; 100 struct brw_gs_unit_state *gs = intel->batch.bo->virtual + offset; 116 struct brw_clip_unit_state *clip = intel->batch.bo->virtual + offset; 136 struct brw_sf_unit_state *sf = intel->batch.bo->virtual + offset; 153 struct brw_wm_unit_state *wm = intel->batch.bo->virtual + offset; 180 uint32_t *surf = brw->intel.batch.bo->virtual + offset; 204 struct gen7_surface_state *surf = brw->intel.batch.bo->virtual + offset; 227 struct gen5_sampler_default_color *sdc = (intel->batch.bo->virtual + 242 struct brw_sampler_default_color *sdc = (intel->batch.bo [all...] |
/external/mesa3d/src/mesa/drivers/dri/intel/ |
H A D | intel_regions.c | 127 if (drm_intel_bo_busy(region->bo)) { 137 drm_intel_gem_bo_map_gtt(region->bo); 139 drm_intel_bo_map(region->bo, true); 141 region->map = region->bo->virtual; 157 drm_intel_gem_bo_unmap_gtt(region->bo); 159 drm_intel_bo_unmap(region->bo); 184 region->bo = buffer; 226 if (drm_intel_bo_flink(region->bo, ®ion->name)) 321 drm_intel_bo_unreference(region->bo); 394 src_pitch, src->bo, src_offse [all...] |
/external/libdrm/radeon/ |
H A D | radeon_cs_int.h | 6 struct radeon_bo_int *bo; member in struct:radeon_cs_space_check 39 struct radeon_bo *bo,
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H A D | radeon_cs_gem.c | 173 struct radeon_bo *bo, 178 struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; 188 /* in one CS a bo can only be in read or write domain but not 200 if this bo is for sure not in this cs.*/ 201 if ((atomic_read((atomic_t *)radeon_gem_get_reloc_in_cs(bo)) & cs->id)) { 202 /* check if bo is already referenced. 204 * it often relocates same shared dma bo again. */ 209 if (reloc->handle == bo->handle) { 262 reloc->handle = bo->handle; 267 radeon_bo_ref(bo); 172 cs_gem_write_reloc(struct radeon_cs_int *cs, struct radeon_bo *bo, uint32_t read_domain, uint32_t write_domain, uint32_t flags) argument 341 bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root; local [all...] |
/external/mesa3d/src/gallium/drivers/nouveau/ |
H A D | nouveau_mm.c | 37 struct nouveau_bo *bo; member in struct:mm_slab 99 /* size of bo allocation for slab with chunks of (1 << chunk_order) bytes */ 129 slab->bo = NULL; 132 &slab->bo); 155 /* @return token to identify slab or NULL if we just allocated a new bo */ 158 uint32_t size, struct nouveau_bo **bo, uint32_t *offset) 168 bo); 195 nouveau_bo_ref(slab->bo, bo); 266 nouveau_bo_ref(NULL, &slab->bo); 157 nouveau_mm_allocate(struct nouveau_mman *cache, uint32_t size, struct nouveau_bo **bo, uint32_t *offset) argument [all...] |
/external/mesa3d/src/gbm/backends/dri/ |
H A D | gbm_driint.h | 94 gbm_dri_bo(struct gbm_bo *bo) argument 96 return (struct gbm_dri_bo *) bo;
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/external/mesa3d/src/mesa/drivers/dri/nouveau/ |
H A D | nv10_state_fb.c | 64 if (!nfb->hierz.bo || nfb->hierz.bo->size != size) { 70 nouveau_bo_ref(NULL, &nfb->hierz.bo); 72 &config, &nfb->hierz.bo); 78 nfb->hierz.bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 128 s->bo, 0, bo_flags); 141 s->bo, 0, bo_flags); 208 if (nfb->hierz.bo) {
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H A D | nv04_surface.c | 200 { src->bo, NOUVEAU_BO_RD | NOUVEAU_BO_VRAM | NOUVEAU_BO_GART }, 201 { dst->bo, NOUVEAU_BO_WR | NOUVEAU_BO_VRAM }, 239 PUSH_RELOC(push, dst->bo, dst->offset, NOUVEAU_BO_LOW, 0, 0); 242 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); 261 PUSH_RELOC(push, src->bo, src->offset + (y + sy) * src->pitch + 281 { src->bo, NOUVEAU_BO_RD | NOUVEAU_BO_VRAM | NOUVEAU_BO_GART }, 282 { dst->bo, NOUVEAU_BO_WR | NOUVEAU_BO_VRAM | NOUVEAU_BO_GART }, 298 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); 299 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); 301 PUSH_RELOC(push, src->bo, sr [all...] |
/external/libdrm/nouveau/ |
H A D | bufctx.c | 128 struct nouveau_bo *bo, uint32_t flags) 140 pref->base.bo = bo; 155 struct nouveau_bo *bo, uint64_t data, uint32_t flags, 160 struct nouveau_bufref *bref = nouveau_bufctx_refn(bctx, bin, bo, flags); 127 nouveau_bufctx_refn(struct nouveau_bufctx *bctx, int bin, struct nouveau_bo *bo, uint32_t flags) argument 154 nouveau_bufctx_mthd(struct nouveau_bufctx *bctx, int bin, uint32_t packet, struct nouveau_bo *bo, uint64_t data, uint32_t flags, uint32_t vor, uint32_t tor) argument
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/external/mesa3d/src/gallium/winsys/radeon/drm/ |
H A D | radeon_drm_cs.c | 210 int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo) argument 214 unsigned hash = bo->handle & (sizeof(csc->is_handle_added)-1); 219 if (reloc->handle == bo->handle) { 227 if (reloc->handle == bo->handle) { 238 /*printf("write_reloc collision, hash: %i, handle: %i\n", hash, bo->handle);*/ 248 struct radeon_bo *bo, 255 unsigned hash = bo->handle & (sizeof(csc->is_handle_added)-1); 262 if (reloc->handle == bo->handle) { 271 if (reloc->handle == bo->handle) { 275 /*printf("write_reloc collision, hash: %i, handle: %i\n", hash, bo 247 radeon_add_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo, enum radeon_bo_usage usage, enum radeon_bo_domain domains, enum radeon_bo_domain *added_domains) argument 320 struct radeon_bo *bo = (struct radeon_bo*)buf; local 383 struct radeon_bo *bo = (struct radeon_bo*)buf; local 538 struct radeon_bo *bo = (struct radeon_bo*)_buf; local [all...] |
/external/skia/src/images/ |
H A D | SkJpegUtility.cpp | 28 size_t bo = (size_t) byte_offset; local 30 if (bo > src->current_offset) { 31 (void)src->fStream->skip(bo - src->current_offset); 38 (void)src->fStream->skip(bo); 41 src->current_offset = bo;
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/external/mesa3d/src/gallium/drivers/nvc0/ |
H A D | nvc0_query.c | 40 struct nouveau_bo *bo; member in struct:nvc0_query 64 if (q->bo) { 65 nouveau_bo_ref(NULL, &q->bo); 75 q->mm = nouveau_mm_allocate(screen->base.mm_GART, size, &q->bo, &q->base); 76 if (!q->bo) 80 ret = nouveau_bo_map(q->bo, 0, screen->base.client); 85 q->data = (uint32_t *)((uint8_t *)q->bo->map + q->base); 163 PUSH_REFN (push, q->bo, NOUVEAU_BO_GART | NOUVEAU_BO_WR); 165 PUSH_DATAh(push, q->bo->offset + offset); 166 PUSH_DATA (push, q->bo [all...] |
/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | radeon_screen.c | 246 image->bo = radeon_bo_open(radeonScreen->bom, 253 if (image->bo == NULL) { 287 radeon_bo_ref(rrb->bo); 288 image->bo = rrb->bo; 300 radeon_bo_unref(image->bo); 346 image->bo = radeon_bo_open(radeonScreen->bom, 353 if (image->bo == NULL) { 369 *value = image->bo->handle; 372 radeon_gem_get_kernel_name(image->bo, (uint32_ [all...] |
H A D | radeon_common_context.c | 352 struct radeon_bo *depth_bo = NULL, *bo; local 469 if (rb->bo) { 470 uint32_t name = radeon_gem_name_bo(rb->bo); 490 bo = depth_bo; 491 radeon_bo_ref(bo); 496 bo = radeon_bo_open(radeon->radeonScreen->bom, 503 if (bo == NULL) { 509 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch); 514 radeon_bo_unref(bo); 515 bo [all...] |
/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_screen.c | 246 image->bo = radeon_bo_open(radeonScreen->bom, 253 if (image->bo == NULL) { 287 radeon_bo_ref(rrb->bo); 288 image->bo = rrb->bo; 300 radeon_bo_unref(image->bo); 346 image->bo = radeon_bo_open(radeonScreen->bom, 353 if (image->bo == NULL) { 369 *value = image->bo->handle; 372 radeon_gem_get_kernel_name(image->bo, (uint32_ [all...] |
H A D | radeon_common_context.c | 352 struct radeon_bo *depth_bo = NULL, *bo; local 469 if (rb->bo) { 470 uint32_t name = radeon_gem_name_bo(rb->bo); 490 bo = depth_bo; 491 radeon_bo_ref(bo); 496 bo = radeon_bo_open(radeon->radeonScreen->bom, 503 if (bo == NULL) { 509 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch); 514 radeon_bo_unref(bo); 515 bo [all...] |
H A D | radeon_blit.c | 96 struct radeon_bo *bo, 143 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 145 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) 170 OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 176 struct radeon_bo *bo, 211 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 214 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) 226 OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); 228 OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); 394 "offset [%d x %d], format %s, bo 94 emit_tx_setup(struct r100_context *r100, gl_format mesa_format, struct radeon_bo *bo, intptr_t offset, unsigned width, unsigned height, unsigned pitch) argument 175 emit_cb_setup(struct r100_context *r100, struct radeon_bo *bo, intptr_t offset, gl_format mesa_format, unsigned pitch, unsigned width, unsigned height) argument [all...] |