/external/mesa3d/src/gallium/drivers/svga/ |
H A D | svga_tgsi_insn.c | 924 writemask(temp, channel), 1052 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_XY), src0 )) 1075 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0)) 1100 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 )) 1134 writemask( temp0, dst.mask ), src0, one, zero )) 1139 writemask( temp1, dst.mask ), negate( src0 ), negate( one ), 1198 writemask( temp, TGSI_WRITEMASK_XYZ ), 1213 writemask( temp, TGSI_WRITEMASK_XYZ ), 1502 writemask( tmp, TGSI_WRITEMASK_W ), 1597 writemask(ds [all...] |
H A D | svga_context.h | 93 uint8_t writemask; member in struct:svga_blend_state::__anon12365 124 /* SVGA3D has one ref/mask/writemask triple shared between front &
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H A D | svga_pipe_blend.c | 198 blend->rt[i].writemask = templ->rt[0].colormask;
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/external/mesa3d/src/gallium/auxiliary/tgsi/ |
H A D | tgsi_dump.c | 191 uint writemask ) 193 if (writemask != TGSI_WRITEMASK_XYZW) { 195 if (writemask & TGSI_WRITEMASK_X) 197 if (writemask & TGSI_WRITEMASK_Y) 199 if (writemask & TGSI_WRITEMASK_Z) 201 if (writemask & TGSI_WRITEMASK_W)
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_vec4_reg_allocate.cpp | 339 temp.writemask = 0; 341 temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c)); 342 assert(temp.writemask != 0); 353 * whole register and use spill_reg's writemask to select which
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H A D | brw_vec4_copy_propagation.cpp | 279 * not get used based on the destination writemask. 311 if (inst->dst.writemask & (1 << i)) { 324 if (inst->dst.writemask & (1 << j) &&
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H A D | brw_vec4_emit.cpp | 66 reg.dw1.bits.writemask = inst->dst.writemask; 165 brw_reg.dw1.bits.writemask = dst.writemask; 171 brw_reg.dw1.bits.writemask = dst.writemask; 285 /* Can't do writemask because math can't be align16. */ 286 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 318 /* Can't do writemask because math can't be align16. */ 319 assert(dst.dw1.bits.writemask [all...] |
H A D | brw_vs_emit.c | 438 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); 464 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); 493 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); 664 dst.dw1.bits.writemask != 0xf) 747 dst.dw1.bits.writemask != 0xf) 824 if (dst.dw1.bits.writemask & WRITEMASK_X) { 847 if (dst.dw1.bits.writemask & WRITEMASK_Y) { 852 if (dst.dw1.bits.writemask & WRITEMASK_Z) { 867 if (dst.dw1.bits.writemask & WRITEMASK_W) { 882 bool need_tmp = (dst.dw1.bits.writemask ! [all...] |
H A D | brw_eu.h | 90 GLuint writemask:4; /* dest only, align16 only */ member in struct:brw_reg::__anon12598::__anon12599 184 * \param writemask WRITEMASK_X/Y/Z/W bitfield 194 GLuint writemask ) 217 * set swizzle and writemask to W, as the lower bits of subnr will 223 reg.dw1.bits.writemask = writemask; 531 /* If/else instructions break in align16 mode if writemask & swizzle 693 reg.dw1.bits.writemask &= mask; 701 reg.dw1.bits.writemask = mask; 967 GLuint writemask, [all...] |
H A D | brw_vec4.h | 136 dst_reg(register_file file, int reg, const glsl_type *type, int writemask); 142 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:brw::dst_reg
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H A D | brw_eu_emit.c | 128 insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask; 785 insn->bits1.da3src.dest_writemask = dest.dw1.bits.writemask; 2303 GLuint writemask, 2314 if (writemask == 0) { 2315 /*printf("%s: zero writemask??\n", __FUNCTION__); */ 2325 * information and use it to modify the writemask for the 2329 if (writemask != WRITEMASK_XYZW) { 2334 if (writemask & (1<<i)) 2339 if (!(writemask & (1<<i))) 2345 if (newmask != writemask) { 2297 brw_SAMPLE(struct brw_compile *p, struct brw_reg dest, GLuint msg_reg_nr, struct brw_reg src0, GLuint binding_table_index, GLuint sampler, GLuint writemask, GLuint msg_type, GLuint response_length, GLuint msg_length, GLuint header_present, GLuint simd_mode, GLuint return_format) argument [all...] |
/external/mesa3d/src/gallium/drivers/llvmpipe/ |
H A D | lp_state_blend.c | 119 state->depth.writemask = 0;
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H A D | lp_state_fs.c | 276 if (!(key->depth.enabled && key->depth.writemask) && 277 !(key->stencil[0].enabled && key->stencil[0].writemask)) 505 if (!(key->depth.enabled && key->depth.writemask) && 506 !(key->stencil[0].enabled && key->stencil[0].writemask)) 1135 debug_printf("depth.writemask = %u\n", key->depth.writemask); 1145 debug_printf("stencil[%u].writemask = 0x%x\n", i, key->stencil[i].writemask);
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_compiler.h | 106 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask);
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H A D | radeon_compiler.c | 168 * writemask is honoured. 170 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask) argument 182 inst->U.I.DstReg.WriteMask &= writemask;
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_state.h | 61 uint8_t writemask[2]; member in struct:si_state_dsa
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/external/mesa3d/src/gallium/drivers/r600/ |
H A D | r600_state_common.c | 250 S_028430_STENCILWRITEMASK(state->writemask[0])); 255 S_028434_STENCILWRITEMASK_BF(state->writemask[1])); 278 ref.writemask[0] = dsa->writemask[0]; 279 ref.writemask[1] = dsa->writemask[1]; 301 ref.writemask[0] = dsa->writemask[0]; 302 ref.writemask[1] = dsa->writemask[ [all...] |
/external/mesa3d/src/gallium/drivers/i915/ |
H A D | i915_state.c | 446 int writemask = depth_stencil->stencil[0].writemask & 0xff; local 452 STENCIL_WRITE_MASK(writemask)); 475 int wmask = depth_stencil->stencil[1].writemask & 0xff; 511 if (depth_stencil->depth.writemask)
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H A D | i915_fpc_translate.c | 322 * Compute flags for saturation and writemask. 497 uint writemask; local 672 A0_DEST_CHANNEL_ALL, /* dest writemask */ 687 A0_DEST_CHANNEL_ALL, /* dest writemask */ 865 writemask = inst->Dst[0].Register.WriteMask; 867 if (writemask & TGSI_WRITEMASK_Y) { 870 if (writemask & TGSI_WRITEMASK_X) 889 if (writemask & TGSI_WRITEMASK_X) {
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/external/mesa3d/src/gallium/drivers/nv30/ |
H A D | nv30_state.c | 221 SB_DATA (so, cso->depth.writemask); 227 SB_DATA (so, cso->stencil[0].writemask); 243 SB_DATA (so, cso->stencil[1].writemask);
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/external/mesa3d/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_tgsi_aos.c | 327 LLVMValueRef writemask; local 329 writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm, 335 mask = LLVMBuildAnd(builder, mask, writemask, ""); 337 mask = writemask; 471 * assume a full writemask and then let LLVM optimization passes eliminate
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/external/mesa3d/src/gallium/drivers/softpipe/ |
H A D | sp_quad_depth_test.c | 420 * \param wrtMask writemask controlling which bits are changed in the 504 /* apply bit-wise stencil buffer writemask */ 586 /* Update our internal copy only if writemask set. Even if 587 * depth.writemask is FALSE, may still need to write out buffer 590 if (softpipe->depth_stencil->depth.writemask) { 632 wrtMask = softpipe->depth_stencil->stencil[face].writemask; 813 if (qs->softpipe->depth_stencil->depth.writemask) 894 boolean depthwrite = qs->softpipe->depth_stencil->depth.writemask;
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/external/mesa3d/src/gallium/drivers/trace/ |
H A D | tr_dump_state.c | 317 trace_dump_member(bool, &state->depth, writemask); 333 trace_dump_member(uint, &state->stencil[i], writemask);
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/external/mesa3d/src/mesa/state_tracker/ |
H A D | st_cb_clear.c | 258 depth_stencil.depth.writemask = 1; 271 depth_stencil.stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
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/external/mesa3d/src/gallium/auxiliary/postprocess/ |
H A D | pp_mlaa.c | 106 mstencil.stencil[0].valuemask = mstencil.stencil[0].writemask = ~0;
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