| /art/compiler/utils/mips64/ |
| H A D | constants_mips64.h | 62 TIMES_8 = 3 enumerator in enum:art::mips64::ScaleFactor
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| /art/compiler/utils/mips/ |
| H A D | constants_mips.h | 86 TIMES_8 = 3 enumerator in enum:art::mips::ScaleFactor
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| /art/compiler/utils/x86/ |
| H A D | constants_x86.h | 75 TIMES_8 = 3 enumerator in enum:art::x86::ScaleFactor
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| /art/compiler/utils/x86_64/ |
| H A D | constants_x86_64.h | 84 TIMES_8 = 3 enumerator in enum:art::x86_64::ScaleFactor
|
| /art/compiler/utils/arm/ |
| H A D | constants_arm.h | 56 TIMES_8 = 3 enumerator in enum:art::arm::ScaleFactor
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| /art/compiler/optimizing/ |
| H A D | code_generator_mips64.cc | 1352 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
1355 __ Dsll(TMP, index.AsRegister<GpuRegister>(), TIMES_8);
1382 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
1385 __ Dsll(TMP, index.AsRegister<GpuRegister>(), TIMES_8);
1512 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
1515 __ Dsll(TMP, index.AsRegister<GpuRegister>(), TIMES_8);
1544 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
1547 __ Dsll(TMP, index.AsRegister<GpuRegister>(), TIMES_8);
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| H A D | code_generator_x86.cc | 3638 size_t offset = (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
3644 Address(obj, index.AsRegister<Register>(), TIMES_8, data_offset));
3647 Address(obj, index.AsRegister<Register>(), TIMES_8, data_offset + kX86WordSize));
3669 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset));
3671 __ movsd(out, Address(obj, index.AsRegister<Register>(), TIMES_8, data_offset));
3835 size_t offset = (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
3849 __ movl(Address(obj, index.AsRegister<Register>(), TIMES_8, data_offset),
3852 __ movl(Address(obj, index.AsRegister<Register>(), TIMES_8, data_offset + kX86WordSize),
3857 __ movl(Address(obj, index.AsRegister<Register>(), TIMES_8, data_offset),
3860 __ movl(Address(obj, index.AsRegister<Register>(), TIMES_8, data_offse
[all...] |
| H A D | code_generator_arm.cc | 3256 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
3259 __ add(IP, obj, ShifterOperand(index.AsRegister<Register>(), LSL, TIMES_8));
3284 size_t offset = (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
3287 __ add(IP, obj, ShifterOperand(index.AsRegister<Register>(), LSL, TIMES_8));
3407 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
3410 __ add(IP, obj, ShifterOperand(index.AsRegister<Register>(), LSL, TIMES_8));
3435 size_t offset = (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
3438 __ add(IP, obj, ShifterOperand(index.AsRegister<Register>(), LSL, TIMES_8));
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| H A D | code_generator_x86_64.cc | 3509 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset));
3511 __ movq(out, Address(obj, index.AsRegister<CpuRegister>(), TIMES_8, data_offset));
3533 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset));
3535 __ movsd(out, Address(obj, index.AsRegister<CpuRegister>(), TIMES_8, data_offset));
3690 size_t offset = (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
3701 __ movq(Address(obj, index.AsRegister<CpuRegister>(), TIMES_8, data_offset),
3707 __ movq(Address(obj, index.AsRegister<CpuRegister>(), TIMES_8, data_offset),
3733 size_t offset = (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
3738 __ movsd(Address(obj, index.AsRegister<CpuRegister>(), TIMES_8, data_offset),
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