| /external/llvm/include/llvm/Target/ |
| H A D | TargetOpcodes.h | 32 /// KILL - This instruction is a noop that is used only to adjust the
35 KILL = 5, enumerator in enum:llvm::TargetOpcode::__anon10291
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| /external/compiler-rt/test/asan/TestCases/Android/ |
| H A D | coverage-android.cc | 115 #ifdef KILL
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| /external/openssh/ |
| H A D | opensshd.init.in | 9 KILL=@KILL@
50 ${KILL} ${PID}
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| H A D | session.c | 2397 SSH_SIG(KILL);
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| /external/lldb/source/Plugins/Process/Linux/ |
| H A D | LinuxSignals.cpp | 41 ADDSIGNAL(KILL, false, true, true, "kill");
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| /external/llvm/lib/CodeGen/ |
| H A D | ExpandPostRAPseudos.cpp | 103 MI->setDesc(TII->get(TargetOpcode::KILL));
114 MI->setDesc(TII->get(TargetOpcode::KILL));
141 MI->setDesc(TII->get(TargetOpcode::KILL));
151 // No need to insert an identity copy instruction, but replace with a KILL
155 // instruction with KILL.
156 MI->setDesc(TII->get(TargetOpcode::KILL));
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| H A D | MachineCopyPropagation.cpp | 131 // Turn it into a noop KILL instruction as opposed to removing it to
134 MI->setDesc(TII->get(TargetOpcode::KILL));
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| H A D | LiveRangeEdit.cpp | 286 // a KILL instead. This way, the physreg live ranges don't end up
292 MI->setDesc(TII.get(TargetOpcode::KILL));
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| H A D | VirtRegMap.cpp | 424 // Transform identity copy to a KILL to deal with subregisters.
425 MI->setDesc(TII->get(TargetOpcode::KILL));
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| H A D | InlineSpiller.cpp | 808 MI->setDesc(TII.get(TargetOpcode::KILL));
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| /external/llvm/lib/Target/R600/ |
| H A D | R600EmitClauseMarkers.cpp | 48 case AMDGPU::KILL:
94 case AMDGPU::KILL:
255 // * KILL or INTERP instructions
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| H A D | R600ControlFlowFinalizer.cpp | 227 case AMDGPU::KILL:
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| H A D | R600MCCodeEmitter.cpp | 97 MI.getOpcode() == AMDGPU::KILL) {
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonNewValueJump.cpp | 127 // %R0<def> = KILL %R0, %D0<imp-use,kill>
129 // Hence, we need to check if it's a KILL instruction.
130 if (II->getOpcode() == TargetOpcode::KILL)
187 // KILL sets kill flag on the opcode. It also sets up a
190 // %R0<def> = KILL %R0, %D0<imp-use,kill>
194 if (MII->getOpcode() == TargetOpcode::KILL ||
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| H A D | HexagonMachineScheduler.cpp | 110 case TargetOpcode::KILL:
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 758 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
815 case TargetOpcode::KILL:
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 305 case TargetOpcode::KILL:
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| /external/libvncserver/webclients/java-applet/ssl/ |
| H A D | ss_vncviewer | 811 kill -KILL "$pssh" 2>/dev/null
819 kill -KILL "$stunnel_pid" 2>/dev/null
827 kill -KILL "$dsm_pid" 2>/dev/null
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| /external/libvncserver/x11vnc/misc/enhanced_tightvnc_viewer/bin/util/ |
| H A D | ss_vncviewer | 808 kill -KILL "$pssh" 2>/dev/null
816 kill -KILL "$stunnel_pid" 2>/dev/null
824 kill -KILL "$dsm_pid" 2>/dev/null
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| H A D | R600MCCodeEmitter.cpp | 158 MI.getOpcode() == AMDGPU::KILL) {
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 396 // %W1<def> = KILL %W1, %X1<imp-def>
414 TII->get(TargetOpcode::KILL), DstRegW)
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| /external/toybox/lib/ |
| H A D | lib.c | 627 SIGNIFY(FPE), SIGNIFY(HUP), SIGNIFY(ILL), SIGNIFY(INT), SIGNIFY(KILL),
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 545 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2647 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2655 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2682 assert(ARM::KILL != Opc && "Invalid table entry");
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| /external/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 1642 DEBUG(dbgs() << "Inserting dummy KILL\n");
1643 Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
|