| /external/libhevc/common/arm/ |
| H A D | ihevc_sao_band_offset_luma.s | 100 VDUP.8 D31,r11 @band_pos
118 VADD.I8 D5,D1,D31 @band_table.val[0] = vadd_u8(band_table.val[0], band_pos)
121 VADD.I8 D6,D2,D31 @band_table.val[1] = vadd_u8(band_table.val[1], band_pos)
124 VADD.I8 D7,D3,D31 @band_table.val[2] = vadd_u8(band_table.val[2], band_pos)
127 VADD.I8 D8,D4,D31 @band_table.val[3] = vadd_u8(band_table.val[3], band_pos)
200 VSUB.I8 D14,D13,D31 @vsub_u8(au1_cur_row, band_pos)
203 VSUB.I8 D16,D15,D31 @vsub_u8(au1_cur_row, band_pos)
206 VSUB.I8 D18,D17,D31 @vsub_u8(au1_cur_row, band_pos)
209 VSUB.I8 D20,D19,D31 @vsub_u8(au1_cur_row, band_pos)
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| H A D | ihevc_sao_band_offset_chroma.s | 110 VDUP.8 D31,r6 @band_pos_u
124 VADD.I8 D5,D1,D31 @band_table_u.val[0] = vadd_u8(band_table_u.val[0], sao_band_pos_u)
127 VADD.I8 D6,D2,D31 @band_table_u.val[1] = vadd_u8(band_table_u.val[1], sao_band_pos_u)
130 VADD.I8 D7,D3,D31 @band_table_u.val[2] = vadd_u8(band_table_u.val[2], sao_band_pos_u)
133 VADD.I8 D8,D4,D31 @band_table_u.val[3] = vadd_u8(band_table_u.val[3], sao_band_pos_u)
290 VSUB.I8 D7,D5,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
296 VSUB.I8 D15,D13,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
302 VSUB.I8 D19,D17,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
308 VSUB.I8 D23,D21,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
344 VSUB.I8 D7,D5,D31
[all...] |
| H A D | ihevc_sao_edge_offset_class1.s | 131 VLD1.8 D31,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
149 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
214 VMOVN.I16 D31,Q14 @II vmovn_s16(pi2_tmp_cur_row.val[1])
249 VMOVN.I16 D31,Q14 @vmovn_s16(pi2_tmp_cur_row.val[1])
291 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
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| H A D | ihevc_sao_edge_offset_class1_chroma.s | 136 VLD1.8 D31,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
154 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
227 VMOVN.I16 D31,Q14 @II vmovn_s16(pi2_tmp_cur_row.val[1])
267 VMOVN.I16 D31,Q14 @vmovn_s16(pi2_tmp_cur_row.val[1])
309 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
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| H A D | ihevc_sao_edge_offset_class0_chroma.s | 157 VLD1.8 D31,[r12] @II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)
258 VMOVL.U8 Q15,D31 @II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vmovl_u8(vget_high_u8(pu1_cur_row)))
320 VLD1.8 D31,[r12] @II pu1_cur_row = vld1q_u8(pu1_src_cpy)
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| H A D | ihevc_sao_edge_offset_class0.s | 231 VTBL.8 D31,{D11},D29 @II offset = vtbl1_s8(offset_tbl, vget_high_s8(edge_idx))
244 VADDW.S8 Q14,Q14,D31 @II pi2_tmp_cur_row.val[1] = vaddw_s8(pi2_tmp_cur_row.val[1], offset)
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| H A D | ihevc_sao_edge_offset_class2.s | 341 VLD1.8 D31,[r11] @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
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| H A D | ihevc_sao_edge_offset_class2_chroma.s | 448 VLD1.8 D31,[r11] @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
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| H A D | ihevc_sao_edge_offset_class3.s | 357 VLD1.8 D31,[r2] @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
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| H A D | ihevc_sao_edge_offset_class3_chroma.s | 451 VLD1.8 D31,[r4] @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
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| /external/libhevc/decoder/arm/ |
| H A D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 166 VLD2.8 {D30,D31},[R0]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row 1
222 VADDW.U8 Q10,Q4,D31 @//Q10 - HAS Y + B
223 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
224 VADDW.U8 Q12,Q6,D31 @//Q12 - HAS Y + G
269 VLD2.8 {D30,D31},[R0]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row 1
353 VADDW.U8 Q10,Q4,D31 @//Q10 - HAS Y + B
354 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
355 VADDW.U8 Q12,Q6,D31 @//Q12 - HAS Y + G
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| /external/llvm/test/MC/MachO/ |
| H A D | x86_32-symbols.s | 98 D31: label
949 // CHECK: ('_string', 'D31')
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| H A D | x86_64-symbols.s | 98 D31: label
385 // CHECK-NEXT: Name: D31 (131)
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 79 case AArch64::D31:
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| /external/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 94 SP::D14, SP::D30, SP::D15, SP::D31 };
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| /external/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 142 case AArch64::D31: return AArch64::B31;
182 case AArch64::B31: return AArch64::D31;
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 145 // Reserve D16-D31 if the subtarget doesn't support them.
147 assert(ARM::D31 == ARM::D16 + 15);
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| H A D | ARMFrameLowering.cpp | 602 if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 119 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
|
| /external/valgrind/memcheck/ |
| H A D | mc_machine.c | 905 if (o >= GOF(D31) && o+sz <= GOF(D31)+SZB(D31)) return GOF(D31);
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 283 AArch64::D30, AArch64::D31
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1024 ARM::D28, ARM::D29, ARM::D30, ARM::D31
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 3034 // Some FPUs only have 16 D registers, so D16-D31 are invalid
3035 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
|