Searched refs:DefMCID (Results 1 - 2 of 2) sorted by relevance

/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h301 const MCInstrDesc &DefMCID,
305 const MCInstrDesc &DefMCID,
317 const MCInstrDesc &DefMCID,
H A DARMBaseInstrInfo.cpp2620 const MCInstrDesc &DefMCID = DefMI->getDesc(); local
2621 if (DefMCID.hasOptionalDef()) {
2622 unsigned NumOps = DefMCID.getNumOperands();
3122 const MCInstrDesc &DefMCID,
3125 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3140 switch (DefMCID.getOpcode()) {
3163 const MCInstrDesc &DefMCID,
3166 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3267 const MCInstrDesc &DefMCID,
3271 unsigned DefClass = DefMCID
3121 getVLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument
3162 getLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument
3266 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument
3432 adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr *DefMI, const MCInstrDesc *DefMCID, unsigned DefAlign) argument
3623 const MCInstrDesc *DefMCID = &DefMI->getDesc(); local
3708 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); local
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