Searched refs:DefMI (Results 1 - 25 of 34) sorted by relevance

12

/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, argument
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
45 MachineInstr *DefMI = LastMI; local
60 DefMI = &*I;
64 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
66 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
H A DMLxExpansionPass.cpp95 MachineInstr *DefMI = MRI->getVRegDef(Reg); local
97 if (DefMI->getParent() != MBB)
99 if (DefMI->isCopyLike()) {
100 Reg = DefMI->getOperand(1).getReg();
102 DefMI = MRI->getVRegDef(Reg);
105 } else if (DefMI->isInsertSubreg()) {
106 Reg = DefMI->getOperand(2).getReg();
108 DefMI = MRI->getVRegDef(Reg);
114 return DefMI;
149 MachineInstr *DefMI local
[all...]
H A DARMBaseInstrInfo.h270 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
277 const MachineInstr *DefMI, unsigned DefIdx,
333 const MachineInstr *DefMI, unsigned DefIdx,
337 const MachineInstr *DefMI,
H A DARMBaseInstrInfo.cpp1847 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); local
1848 bool Invert = !DefMI;
1849 if (!DefMI)
1850 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1851 if (!DefMI)
1861 // Create a new predicated version of DefMI.
1864 DefMI->getDesc(), DestReg);
1866 // Copy all the DefMI operands, excluding its (null) predicate.
1867 const MCInstrDesc &DefDesc = DefMI->getDesc();
1870 NewMI.addOperand(DefMI
2606 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument
3432 adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr *DefMI, const MCInstrDesc *DefMCID, unsigned DefAlign) argument
3613 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
4005 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
4027 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument
[all...]
/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp155 const MachineInstr *DefMI, unsigned DefOperIdx,
159 return TII->defaultDefLatency(SchedModel, DefMI);
164 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
168 unsigned DefClass = DefMI->getDesc().getSchedClass();
175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
183 TII->defaultDefLatency(SchedModel, DefMI));
187 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
211 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
212 && !DefMI
154 computeOperandLatency( const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const argument
217 << *DefMI; local
276 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const argument
[all...]
H A DLiveRangeEdit.cpp52 const MachineInstr *DefMI,
54 assert(DefMI && "Missing instruction");
56 if (!TII.isTriviallyReMaterializable(DefMI, aa))
66 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); local
67 if (!DefMI)
69 checkRematerializable(VNI, DefMI, aa);
166 MachineInstr *DefMI = nullptr, *UseMI = nullptr; local
172 if (DefMI && DefMI != MI)
176 DefMI
51 checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *aa) argument
[all...]
H A DMachineTraceMetrics.cpp608 const MachineInstr *DefMI;
612 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp)
613 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {}
621 DefMI = DefI->getParent();
761 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
763 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()];
766 unsigned Len = LIR.Height + Cycles[DefMI].Depth;
835 BlockInfo[Dep.DefMI->getParent()->getNumber()];
840 unsigned DepCycle = Cycles.lookup(Dep.DefMI)
[all...]
H A DTargetInstrInfo.cpp770 const MachineInstr *DefMI) const {
771 if (DefMI->isTransient())
773 if (DefMI->mayLoad())
775 if (isHighLatencyDef(DefMI->getOpcode()))
797 const MachineInstr *DefMI,
802 unsigned DefClass = DefMI->getDesc().getSchedClass();
807 /// Both DefMI and UseMI must be valid. By default, call directly to the
811 const MachineInstr *DefMI, unsigned DefIdx,
813 unsigned DefClass = DefMI->getDesc().getSchedClass();
822 const MachineInstr *DefMI) cons
796 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument
810 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
847 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
[all...]
H A DInlineSpiller.cpp113 MachineInstr *DefMI; member in struct:__anon10419::InlineSpiller::SibValueInfo
124 SpillReg(Reg), SpillVNI(VNI), SpillMBB(nullptr), DefMI(nullptr) {}
127 bool hasDef() const { return DefByOrigPHI || DefMI; }
335 if (SVI.DefMI)
336 OS << " def: " << *SVI.DefMI;
399 DepSV.DefMI = SV.DefMI;
500 return SVI->second.DefMI;
621 SVI->second.DefMI = MI;
642 return SVI->second.DefMI;
665 MachineInstr *DefMI = nullptr; local
740 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def); local
[all...]
H A DRegisterCoalescer.cpp644 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
645 if (!DefMI)
647 if (!DefMI->isCommutable())
649 // If DefMI is a two-address instruction then commuting it will change the
651 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
654 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
657 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
666 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
691 << *DefMI);
695 MachineBasicBlock *MBB = DefMI
1787 computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const argument
1872 const MachineInstr *DefMI = nullptr; local
[all...]
H A DMachineCSE.cpp133 MachineInstr *DefMI = MRI->getVRegDef(Reg); local
134 if (!DefMI->isCopy())
136 unsigned SrcReg = DefMI->getOperand(1).getReg();
139 if (DefMI->getOperand(0).getSubReg())
153 if (DefMI->getOperand(1).getSubReg())
158 DEBUG(dbgs() << "Coalescing: " << *DefMI);
165 DefMI->eraseFromParent();
H A DPHIElimination.cpp158 for (MachineInstr *DefMI : ImpDefs) {
159 unsigned DefReg = DefMI->getOperand(0).getReg();
162 LIS->RemoveMachineInstrFromMaps(DefMI);
163 DefMI->eraseFromParent();
395 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
396 if (DefMI->isImplicitDef())
397 ImpDefs.insert(DefMI);
H A DEarlyIfConversion.cpp245 MachineInstr *DefMI = MRI->getVRegDef(Reg); local
246 if (!DefMI || DefMI->getParent() != Head)
248 if (InsertAfter.insert(DefMI).second)
249 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
250 if (DefMI->isTerminator()) {
H A DTwoAddressInstructionPass.cpp320 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
321 if (DefMI.getParent() != BB || DefMI.isDebugValue())
324 Ret = &DefMI;
325 else if (Ret != &DefMI)
449 MachineInstr *DefMI = &MI; local
455 if (!isPlainlyKilled(DefMI, Reg, LIS))
464 DefMI = Begin->getParent();
469 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
991 for (MachineInstr &DefMI
[all...]
H A DMachineSink.cpp162 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
163 if (DefMI->isCopyLike())
165 DEBUG(dbgs() << "Coalescing: " << *DefMI);
373 MachineInstr *DefMI = MRI->getVRegDef(Reg); local
374 if (DefMI->getParent() == MI->getParent())
H A DPeepholeOptimizer.cpp1163 MachineInstr *DefMI = nullptr; local
1166 DefMI);
1169 // DefMI.
1173 LocalMIs.erase(DefMI);
1176 DefMI->eraseFromParent();
/external/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp261 MachineInstr *DefMI = MRI.getVRegDef(Reg); local
263 assert(DefMI);
265 // See if DefMI is an instruction that loads from a GOT entry that holds the
267 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3)
270 unsigned Flags = DefMI->getOperand(2).getTargetFlags();
276 assert(DefMI->hasOneMemOperand());
277 Val = (*DefMI->memoperands_begin())->getValue();
279 Val = (*DefMI->memoperands_begin())->getPseudoValue();
/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h153 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
175 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
H A DMachineTraceMetrics.h292 /// is part of the trace of the user instruction. It is assumed that DefMI
294 bool isDepInTrace(const MachineInstr *DefMI,
314 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
H A DLiveRangeEdit.h167 /// values if DefMI may be rematerializable.
168 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
/external/llvm/lib/Target/X86/
H A DX86CallFrameOptimization.cpp462 MachineBasicBlock::iterator DefMI = MRI->getVRegDef(Reg);
466 if (DefMI->getOpcode() != X86::MOV32rm ||
467 DefMI->getParent() != FrameSetup->getParent())
475 for (auto I = DefMI; I != FrameSetup; ++I)
479 return DefMI;
H A DX86InstrInfo.h425 const MachineInstr *DefMI, unsigned DefIdx,
448 /// defined by the load we are trying to fold. DefMI returns the machine
454 MachineInstr *&DefMI) const override;
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h988 /// defined by the load we are trying to fold. DefMI returns the machine
994 MachineInstr *&DefMI) const {
1001 /// then the caller may assume that DefMI has been erased from its parent
1004 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, argument
1037 const MachineInstr *DefMI, unsigned DefIdx,
1044 const MachineInstr *DefMI, unsigned DefIdx,
1062 const MachineInstr *DefMI) const;
1065 const MachineInstr *DefMI) const;
1079 const MachineInstr *DefMI, unsigned DefIdx,
1088 const MachineInstr *DefMI, unsigne
1077 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h99 const MachineInstr *DefMI, unsigned DefIdx,
110 const MachineInstr *DefMI,
178 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp296 const MachineInstr *DefMI = MRI.getVRegDef(VReg); local
297 if (!DefMI->isFullCopy())
299 VReg = DefMI->getOperand(1).getReg();
314 const MachineInstr *DefMI = MRI.getVRegDef(VReg); local
317 switch (DefMI->getOpcode()) {
321 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
327 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
328 DefMI->getOperand(3).getImm() != 0)
337 unsigned ZReg = removeCopies(MRI, DefMI
[all...]

Completed in 3586 milliseconds

12