/external/llvm/lib/Target/ARM/ |
H A D | ARMOptimizeBarriersPass.cpp | 40 // The current implementation allows this iif MI does not have any possible 42 static bool CanMovePastDMB(const MachineInstr *MI) { argument 43 return !(MI->mayLoad() || 44 MI->mayStore() || 45 MI->hasUnmodeledSideEffects() || 46 MI->isCall() || 47 MI->isReturn()); 63 for (auto &MI : MBB) { 64 if (MI.getOpcode() == ARM::DMB) { 68 if (MI [all...] |
/external/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86ATTInstPrinter.h | 31 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, 36 bool printAliasInstr(const MCInst *MI, raw_ostream &OS); 37 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, 41 void printInstruction(const MCInst *MI, raw_ostream &OS); 44 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS); 45 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS); 46 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS); 47 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &OS); 48 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS); 49 void printSrcIdx(const MCInst *MI, unsigne 55 printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 59 printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 63 printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 66 printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 69 printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 72 printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 75 printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 78 printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 81 printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 84 printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 87 printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 90 printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 93 printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 96 printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 99 printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 103 printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 106 printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 109 printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 112 printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 115 printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 118 printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 121 printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 124 printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 127 printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 130 printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 133 printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 136 printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument [all...] |
H A D | X86IntelInstPrinter.h | 31 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, 35 void printInstruction(const MCInst *MI, raw_ostream &O); 38 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 39 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O); 40 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O); 41 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O); 42 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); 43 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); 44 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O); 45 void printDstIdx(const MCInst *MI, unsigne 49 printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 53 printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 58 printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 62 printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 66 printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 70 printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 74 printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 78 printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 82 printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 86 printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 90 printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 94 printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 98 printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 102 printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 106 printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 112 printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 116 printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 120 printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 124 printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 128 printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 132 printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 136 printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 140 printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 144 printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 148 printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 152 printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 156 printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument [all...] |
H A D | X86InstComments.cpp | 28 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
argument 29 switch (MI->getOpcode()) {
117 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
argument 123 switch (MI->getOpcode()) {
130 Src2Name = getRegName(MI->getOperand(2).getReg());
134 if(MI->getOperand(MI->getNumOperands()-1).isImm())
136 MI->getOperand(MI->getNumOperands()-1).getImm(),
138 Src1Name = getRegName(MI [all...] |
/external/llvm/lib/Target/R600/InstPrinter/ |
H A D | AMDGPUInstPrinter.h | 29 void printInstruction(const MCInst *MI, raw_ostream &O); 32 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, 38 void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 39 void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 40 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 41 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 42 void printU32ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 43 void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O); 44 void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O); 45 void printAddr64(const MCInst *MI, unsigne [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUCodeEmitter.h | 21 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 22 virtual uint64_t getMachineOpValue(const MachineInstr &MI, argument 24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI, argument 28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI, argument 32 virtual uint64_t VOPPostEncode(const MachineInstr &MI, argument 36 virtual uint64_t i32LiteralEncode(const MachineInstr &MI, argument 40 virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo) argument
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/external/llvm/lib/Target/PowerPC/InstPrinter/ |
H A D | PPCInstPrinter.h | 35 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, 39 void printInstruction(const MCInst *MI, raw_ostream &O); 43 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 44 void printPredicateOperand(const MCInst *MI, unsigned OpNo, 47 void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 48 void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 49 void printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 50 void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 51 void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 52 void printU5ImmOperand(const MCInst *MI, unsigne [all...] |
/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) { argument 33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); 34 return MI.getOperand(OpNo).getReg() == R; 79 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 81 switch (MI->getOpcode()) { 91 printSaveRestore(MI, O); 96 printSaveRestore(MI, O); 101 printSaveRestore(MI, O); 106 printSaveRestore(MI, O); 112 if (!printAliasInstr(MI, 188 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 205 printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O) argument 214 printUnsignedImm8(const MCInst *MI, int opNum, raw_ostream &O) argument 224 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) argument 249 printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) argument 259 printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) argument 265 printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O) argument 270 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) argument 274 printAlias(const char *Str, const MCInst &MI, unsigned OpNo, raw_ostream &OS) argument 281 printAlias(const char *Str, const MCInst &MI, unsigned OpNo0, unsigned OpNo1, raw_ostream &OS) argument 290 printAlias(const MCInst &MI, raw_ostream &OS) argument 337 printSaveRestore(const MCInst *MI, raw_ostream &O) argument 348 printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | ExpandPostRAPseudos.cpp | 51 bool LowerSubregToReg(MachineInstr *MI); 52 bool LowerCopy(MachineInstr *MI); 54 void TransferImplicitDefs(MachineInstr *MI); 64 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered 66 /// operands from MI to the replacement instruction. 68 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { argument 69 MachineBasicBlock::iterator CopyMI = MI; 72 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 73 MachineOperand &MO = MI->getOperand(i); 80 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { argument 137 LowerCopy(MachineInstr *MI) argument 195 MachineInstr *MI = mi; local [all...] |
H A D | AntiDepBreaker.h | 50 virtual void Observe(MachineInstr *MI, unsigned Count, 58 void UpdateDbgValue(MachineInstr *MI, unsigned OldReg, unsigned NewReg) { argument 59 assert (MI->isDebugValue() && "MI is not DBG_VALUE!"); 60 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg) 61 MI->getOperand(0).setReg(NewReg);
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/external/llvm/lib/Target/SystemZ/InstPrinter/ |
H A D | SystemZInstPrinter.h | 30 void printInstruction(const MCInst *MI, raw_ostream &O); 42 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, 47 void printOperand(const MCInst *MI, int OpNum, raw_ostream &O); 48 void printBDAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); 49 void printBDXAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); 50 void printBDLAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); 51 void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); 52 void printU6ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); 53 void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); 54 void printU8ImmOperand(const MCInst *MI, in [all...] |
/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 7 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument 9 printInstruction(MI, OS); 14 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 17 const MCOperand &Op = MI->getOperand(OpNo); 29 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, argument 31 printOperand(MI, OpNo, O);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 105 MachineInstr &MI = *II; local 106 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 109 MachineFunction &MF = *MI.getParent()->getParent(); 123 if (MI.getOpcode() == Hexagon::TFR_FI) 124 MI.setDesc(TII.get(Hexagon::A2_addi)); 127 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && 128 !TII.isSpillPredRegOp(&MI)) { 130 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false, 132 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset); 135 if (!TII.isValidOffset(MI [all...] |
H A D | HexagonMachineFunctionInfo.h | 48 void addAllocaAdjustInst(MachineInstr* MI) { argument 49 AllocaAdjustInsts.push_back(MI); 58 void setStartPacket(MachineInstr* MI) { argument 59 PacketInfo[MI] |= Hexagon::StartPacket; 61 void setEndPacket(MachineInstr* MI) { argument 62 PacketInfo[MI] |= Hexagon::EndPacket; 64 bool isStartPacket(const MachineInstr* MI) const { 65 return (PacketInfo.count(MI) && 66 (PacketInfo.find(MI)->second & Hexagon::StartPacket)); 68 bool isEndPacket(const MachineInstr* MI) cons [all...] |
H A D | HexagonInstrInfo.h | 50 unsigned isLoadFromStackSlot(const MachineInstr *MI, 58 unsigned isStoreToStackSlot(const MachineInstr *MI, 74 bool analyzeCompare(const MachineInstr *MI, 108 /// into real instructions. The target can edit MI in place, or it can insert 109 /// new instructions and erase MI. The function should return true if 111 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; 113 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 117 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 125 bool isBranch(const MachineInstr *MI) const; 126 bool isPredicable(MachineInstr *MI) cons [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SILowerControlFlow.cpp | 78 void SkipIfDead(MachineInstr &MI); 80 void If(MachineInstr &MI); 81 void Else(MachineInstr &MI); 82 void Break(MachineInstr &MI); 83 void IfBreak(MachineInstr &MI); 84 void ElseBreak(MachineInstr &MI); 85 void Loop(MachineInstr &MI); 86 void EndCf(MachineInstr &MI); 88 void Kill(MachineInstr &MI); 89 void Branch(MachineInstr &MI); 146 SkipIfDead(MachineInstr &MI) argument 180 If(MachineInstr &MI) argument 198 Else(MachineInstr &MI) argument 217 Break(MachineInstr &MI) argument 231 IfBreak(MachineInstr &MI) argument 246 ElseBreak(MachineInstr &MI) argument 261 Loop(MachineInstr &MI) argument 277 EndCf(MachineInstr &MI) argument 290 Branch(MachineInstr &MI) argument 297 Kill(MachineInstr &MI) argument 326 LoadM0(MachineInstr &MI, MachineInstr *MovRel) argument 387 IndirectSrc(MachineInstr &MI) argument 408 IndirectDst(MachineInstr &MI) argument 449 MachineInstr &MI = *I; local [all...] |
H A D | AMDGPUInstrInfo.cpp | 40 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, argument 47 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument 53 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, argument 59 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, argument 65 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, argument 70 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, argument 75 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, argument 92 MachineBasicBlock::iterator MI, 102 MachineBasicBlock::iterator MI, 109 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) cons 91 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 101 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 155 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops, int FrameIndex) const argument 163 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops, MachineInstr *LoadMI) const argument 169 canFoldMemoryOperand(const MachineInstr *MI, ArrayRef<unsigned> Ops) const argument 175 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 247 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonInstPrinter.h | 28 void printInst(MCInst const *MI, raw_ostream &O, StringRef Annot, 31 void printInstruction(const MCInst *MI, raw_ostream &O); 35 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const; 36 void printImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const; 37 void printExtOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const; 38 void printUnsignedImmOperand(const MCInst *MI, unsigned OpNo, 40 void printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) 42 void printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) 44 void printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) 46 void printFrameIndexOperand(const MCInst *MI, unsigne 63 printSymbolHi(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 65 printSymbolLo(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument [all...] |
H A D | HexagonInstPrinter.cpp | 80 void HexagonInstPrinter::printInst(MCInst const *MI, raw_ostream &O, argument 86 if (MI->getOpcode() == Hexagon::ENDLOOP0) { 88 assert(HexagonMCInstrInfo::isPacketEnd(*MI) && "Loop-end must also end the packet"); 90 if (HexagonMCInstrInfo::isPacketBegin(*MI)) { 97 HexagonMCInstrInfo::setPacketBegin (Nop, HexagonMCInstrInfo::isPacketBegin(*MI)); 102 if (HexagonMCInstrInfo::isPacketEnd(*MI)) 105 printInstruction(MI, O); 109 if (HexagonMCInstrInfo::isPacketBegin(*MI)) 112 printInstruction(MI, O); 115 if (HexagonMCInstrInfo::isPacketEnd(*MI)) 124 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 139 printImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 152 printExtOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 171 printUnsignedImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 176 printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 181 printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 186 printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 195 printFrameIndexOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 203 printGlobalOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 210 printJumpTable(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 217 printConstantPool(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 224 printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 231 printCallOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 235 printAbsAddrOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 239 printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 243 printSymbol(const MCInst *MI, unsigned OpNo, raw_ostream &O, bool hi) const argument [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.h | 31 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, 36 virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 38 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 40 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, 51 bool printSysAlias(const MCInst *MI, raw_ostream &O); 53 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 55 void printHexImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 57 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, 60 void printPostIncOperand(const MCInst *MI, unsigned OpNo, argument 62 printPostIncOperand(MI, OpN 87 printMemExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 104 printUImm12Offset(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 110 printAMIndexedWB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/Sparc/InstPrinter/ |
H A D | SparcInstPrinter.cpp | 46 void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 48 if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O)) 49 printInstruction(MI, STI, O); 53 bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, argument 56 switch (MI->getOpcode()) { 60 if (MI->getNumOperands() != 3) 62 if (!MI->getOperand(0).isReg()) 64 switch (MI->getOperand(0).getReg()) { 67 if (MI 107 printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 126 printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) argument 149 printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 173 printGetPCX(const MCInst *MI, unsigned opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.h | 29 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, 34 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 38 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 41 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, 43 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, 46 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, 48 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, 50 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, 52 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, 54 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigne [all...] |
/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 49 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 52 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 55 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 58 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 61 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 64 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, 67 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 70 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 73 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 76 unsigned getSPE2DisEncoding(const MCInst &MI, unsigne 170 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 182 getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 195 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 208 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 220 getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 232 getMemRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 251 getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 270 getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 286 getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 302 getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 318 getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 334 getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 347 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 359 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 28 uint64_t getBinaryCodeForInstr(const MCInst &MI, 31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument 36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, argument 40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, argument 44 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const { argument 47 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, argument 51 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, argument
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 38 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 44 uint64_t getBinaryCodeForInstr(const MCInst &MI, 49 // MO in MI. Fixups is the list of fixups against MI. 50 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 58 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, 61 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, 64 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, 67 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, 70 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigne 84 getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 90 getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 96 getPC16DBLTLSEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 102 getPC32DBLTLSEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 118 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 132 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 143 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 153 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 163 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 174 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 186 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 197 getPCRelEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, unsigned Kind, int64_t Offset, bool AllowTLS) const argument [all...] |