Searched refs:MVT (Results 1 - 25 of 159) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h26 /// MVT - Machine Value Type. Every type that is supported natively by some
28 /// type can be represented by an MVT.
29 class MVT { class in namespace:llvm
126 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
164 LLVM_CONSTEXPR MVT() : SimpleTy(INVALID_SIMPLE_VALUE_TYPE) {} function in class:llvm::MVT
165 LLVM_CONSTEXPR MVT(SimpleValueType SVT) : SimpleTy(SVT) { } function in class:llvm::MVT
167 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
168 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
169 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
170 bool operator!=(const MVT
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H A DValueTypes.h30 /// a MVT can represent.
33 MVT V;
37 LLVM_CONSTEXPR EVT() : V(MVT::INVALID_SIMPLE_VALUE_TYPE), LLVMTy(nullptr) {}
38 LLVM_CONSTEXPR EVT(MVT::SimpleValueType SVT) : V(SVT), LLVMTy(nullptr) {}
39 LLVM_CONSTEXPR EVT(MVT S) : V(S), LLVMTy(nullptr) {}
56 return MVT::getFloatingPointVT(BitWidth);
62 MVT M = MVT::getIntegerVT(BitWidth);
71 MVT M = MVT
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H A DCallingConvLower.h26 class MVT;
70 MVT ValVT;
73 MVT LocVT;
76 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
77 unsigned RegNo, MVT LocVT,
90 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
91 unsigned RegNo, MVT LocVT,
99 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
100 unsigned Offset, MVT LocVT,
113 static CCValAssign getCustomMem(unsigned ValNo, MVT ValV
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/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp86 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
112 static const CostTblEntry<MVT::SimpleValueType>
114 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
115 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
116 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
117 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
127 static const CostTblEntry<MVT::SimpleValueType> AVX512CostTable[] = {
128 { ISD::SHL, MVT::v16i32, 1 },
129 { ISD::SRL, MVT::v16i32, 1 },
130 { ISD::SRA, MVT
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H A DX86CallingConv.h23 inline bool CC_X86_32_VectorCallIndirect(unsigned &ValNo, MVT &ValVT,
24 MVT &LocVT,
29 LocVT = MVT::i32;
36 inline bool CC_X86_AnyReg_Error(unsigned &, MVT &, MVT &,
/external/llvm/lib/IR/
H A DValueTypes.cpp115 case MVT::i1: return "i1";
116 case MVT::i8: return "i8";
117 case MVT::i16: return "i16";
118 case MVT::i32: return "i32";
119 case MVT::i64: return "i64";
120 case MVT::i128: return "i128";
121 case MVT::f16: return "f16";
122 case MVT::f32: return "f32";
123 case MVT::f64: return "f64";
124 case MVT
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/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp55 static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = {
57 { ISD::FP_ROUND, MVT::v2f64, 2 },
58 { ISD::FP_EXTEND, MVT::v2f32, 2 },
59 { ISD::FP_EXTEND, MVT::v4f32, 4 }
64 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
79 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
81 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
82 { ISD::ZERO_EXTEND, MVT::v4i32, MVT
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H A DARMSelectionDAGInfo.cpp53 EVT VT = MVT::i32;
69 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
70 DAG.getConstant(SrcOff, MVT::i32)),
76 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
82 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
83 DAG.getConstant(DstOff, MVT::i32)),
88 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
102 VT = MVT::i16;
105 VT = MVT::i8;
110 DAG.getNode(ISD::ADD, dl, MVT
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/external/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.h23 inline bool CC_PPC_AnyReg_Error(unsigned &, MVT &, MVT &,
H A DPPCFastISel.cpp113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
145 bool isTypeLegal(Type *Ty, MVT &VT);
146 bool isLoadTypeLegal(Type *Ty, MVT &VT);
152 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
155 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
157 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
159 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
161 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT V
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/external/llvm/lib/Target/X86/Utils/
H A DX86ShuffleDecode.h27 class MVT;
39 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
41 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
43 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
45 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
47 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
49 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
51 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
53 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
55 void DecodePSHUFLWMask(MVT, unsigne
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/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp190 static const TypeConversionCostTblEntry<MVT> ConversionTbl[] = {
192 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
194 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
195 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
196 { ISD::UINT_TO_FP, MVT
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H A DAArch64ISelDAGToDAG.cpp255 Val = CurDAG->getTargetConstant(Immed, MVT::i32);
256 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
281 if (N.getValueType() == MVT::i32)
289 return SelectArithImmed(CurDAG->getConstant(Immed, MVT::i32), Val, Shift);
337 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
356 if (!IsLoadStore && SrcVT == MVT::i8)
358 else if (!IsLoadStore && SrcVT == MVT::i16)
360 else if (SrcVT == MVT::i32)
362 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
368 if (!IsLoadStore && SrcVT == MVT
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H A DAArch64FastISel.cpp139 bool isTypeLegal(Type *Ty, MVT &VT);
140 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
144 bool simplifyAddress(Address &Addr, MVT VT);
153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
158 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
161 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
164 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
167 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
172 unsigned emitAddSub_rx(bool UseAdd, MVT RetV
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/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp36 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
38 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
39 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
42 std::string llvm::getName(MVT::SimpleValueType T) {
44 case MVT::Other: return "UNKNOWN";
45 case MVT::iPTR: return "TLI.getPointerTy()";
46 case MVT::iPTRAny: return "TLI.getPointerTy()";
51 std::string llvm::getEnumName(MVT::SimpleValueType T) {
53 case MVT::Other: return "MVT
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/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp436 if (OpVT == MVT::f16) {
437 if (RetVT == MVT::f32)
439 } else if (OpVT == MVT::f32) {
440 if (RetVT == MVT::f64)
442 if (RetVT == MVT::f128)
444 } else if (OpVT == MVT::f64) {
445 if (RetVT == MVT::f128)
455 if (RetVT == MVT::f16) {
456 if (OpVT == MVT::f32)
458 if (OpVT == MVT
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/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp51 (int)MVT::i8,
52 (int)MVT::i16,
53 (int)MVT::i32,
54 (int)MVT::f32,
55 (int)MVT::f64,
56 (int)MVT::i64,
57 (int)MVT::v2i8,
58 (int)MVT::v4i8,
59 (int)MVT::v2i16,
60 (int)MVT
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/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp65 CC_Hexagon(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 CC_Hexagon32(unsigned ValNo, MVT ValVT,
71 MVT LocVT, CCValAssign::LocInfo LocInfo,
75 CC_Hexagon64(unsigned ValNo, MVT ValVT,
76 MVT LocVT, CCValAssign::LocInfo LocInfo,
80 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
81 MVT LocVT, CCValAssign::LocInfo LocInfo,
85 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
86 MVT LocV
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H A DHexagonISelDAGToDAG.cpp112 return CurDAG->getTargetConstant(bitPos, MVT::i32);
138 return CurDAG->getTargetConstant( - Imm, MVT::i32);
145 return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
150 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
156 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
161 return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
166 return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
258 SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
259 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT
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/external/llvm/lib/Target/R600/
H A DSIISelLowering.cpp41 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
42 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
44 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
45 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
47 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
48 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
50 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
51 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
52 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
54 addRegisterClass(MVT
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H A DAMDGPUISelLowering.cpp74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
108 setOperationAction(ISD::Constant, MVT::i32, Legal);
109 setOperationAction(ISD::Constant, MVT::i64, Legal);
110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BRIND, MVT
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp561 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
646 MVT SimpleVT = LoadedVT.getSimpleVT();
664 MVT ScalarVT = SimpleVT.getScalarType();
681 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
685 case MVT::i8:
688 case MVT::i16:
691 case MVT::i32:
694 case MVT::i64:
697 case MVT::f32:
700 case MVT
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/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp76 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
93 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
94 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
95 setOperationAction(ISD::ADDC, MVT::i32, Expand);
96 setOperationAction(ISD::ADDE, MVT::i32, Expand);
97 setOperationAction(ISD::SUBC, MVT::i32, Expand);
98 setOperationAction(ISD::SUBE, MVT::i32, Expand);
101 setOperationAction(ISD::ADD, MVT::i64, Custom);
102 setOperationAction(ISD::SUB, MVT::i64, Custom);
103 setOperationAction(ISD::SMUL_LOHI, MVT
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H A DXCoreISelDAGToDAG.cpp51 return CurDAG->getTargetConstant(Imm, MVT::i32);
92 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
93 Offset = CurDAG->getTargetConstant(0, MVT::i32);
102 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
103 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
120 Reg = CurDAG->getRegister(XCore::CP, MVT::i32);
123 Reg = CurDAG->getRegister(XCore::DP, MVT::i32);
143 MVT::i32, MskSize);
150 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
151 MVT
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/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp105 bool isTypeLegal(Type *Ty, MVT &VT);
106 bool isTypeSupported(Type *Ty, MVT &VT);
107 bool isLoadTypeLegal(Type *Ty, MVT &VT);
114 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
116 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
118 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
120 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
121 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestV
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