Searched refs:OUT_BATCH_REGVAL (Results 1 - 4 of 4) sorted by relevance
/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | r200_blit.c | 80 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, 0); 82 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); 84 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL, (R200_VAP_FORCE_W_TO_ONE | 86 OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL, 0); 87 OUT_BATCH_REGVAL(R200_SE_VTE_CNTL, 0); 88 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0, R200_VTX_XY); 89 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); 90 OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | 169 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | 171 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_ [all...] |
H A D | radeon_cmdbuf.h | 94 #define OUT_BATCH_REGVAL(reg, val) \ macro
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_blit.c | 77 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, 0); 79 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); 82 OUT_BATCH_REGVAL(RADEON_SE_COORD_FMT, (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | 84 OUT_BATCH_REGVAL(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0); 85 OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | 149 OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); 150 OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0, (RADEON_COLOR_ARG_A_ZERO | 155 OUT_BATCH_REGVAL(RADEON_PP_TXABLEND_0, (RADEON_ALPHA_ARG_A_ZERO | 160 OUT_BATCH_REGVAL(RADEON_PP_TXFILTER_0, (RADEON_CLAMP_S_CLAMP_LAST | 164 OUT_BATCH_REGVAL(RADEON_PP_TXFORMAT_ [all...] |
H A D | radeon_cmdbuf.h | 94 #define OUT_BATCH_REGVAL(reg, val) \ macro
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