Searched refs:Op5 (Results 1 - 5 of 5) sorted by relevance
/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); 660 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); 682 unsigned Op1, Op2, Op3, Op4, Op5; local 687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); 695 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 147 MachineOperand &Op5 = MI->getOperand(5); local 157 NewMI->addOperand(Op5);
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/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAG.h | 886 SDValue Op3, SDValue Op4, SDValue Op5);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 5440 SDValue Op3, SDValue Op4, SDValue Op5) { 5441 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 5439 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5915 ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]); local 5920 // If 3rd operand (variable Op5) is a register and the instruction is adds/sub 5923 if (!Op5.isReg() || !((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub")) {
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