Searched refs:Operands (Results 1 - 25 of 62) sorted by relevance

123

/external/llvm/lib/Target/R600/AsmParser/
H A DAMDGPUAsmParser.cpp330 OperandVector &Operands, MCStreamer &Out,
334 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
336 SMLoc NameLoc, OperandVector &Operands) override;
341 OperandVector &Operands,
344 OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands,
349 OperandVector &Operands);
352 void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
353 void cvtDS(MCInst &Inst, const OperandVector &Operands);
354 OperandMatchResultTy parseDSOptionalOps(OperandVector &Operands);
355 OperandMatchResultTy parseDSOff01OptionalOps(OperandVector &Operands);
505 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
545 operandsHaveModifiers(const OperandVector &Operands) argument
559 parseOperand(OperandVector &Operands, StringRef Mnemonic) argument
669 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) argument
749 parseIntWithPrefix(const char *Prefix, OperandVector &Operands, enum AMDGPUOperand::ImmTy ImmTy) argument
764 parseNamedBit(const char *Name, OperandVector &Operands, enum AMDGPUOperand::ImmTy ImmTy) argument
795 operandsHasOptionalOp(const OperandVector &Operands, const OptionalOperand &OOp) argument
808 parseOptionalOps(const ArrayRef<OptionalOperand> &OptionalOps, OperandVector &Operands) argument
857 parseDSOptionalOps(OperandVector &Operands) argument
861 parseDSOff01OptionalOps(OperandVector &Operands) argument
866 parseDSOffsetOptional(OperandVector &Operands) argument
886 cvtDSOffset01(MCInst &Inst, const OperandVector &Operands) argument
914 cvtDS(MCInst &Inst, const OperandVector &Operands) argument
996 parseSWaitCntOps(OperandVector &Operands) argument
1032 parseSOppBrTarget(OperandVector &Operands) argument
1066 parseMubufOptionalOps(OperandVector &Operands) argument
1071 parseOffset(OperandVector &Operands) argument
1076 parseGLC(OperandVector &Operands) argument
1081 parseSLC(OperandVector &Operands) argument
1086 parseTFE(OperandVector &Operands) argument
1094 cvtMubuf(MCInst &Inst, const OperandVector &Operands) argument
1142 parseDMask(OperandVector &Operands) argument
1147 parseUNorm(OperandVector &Operands) argument
1152 parseR128(OperandVector &Operands) argument
1188 isVOP3(OperandVector &Operands) argument
1210 parseVOP3OptionalOps(OperandVector &Operands) argument
1238 cvtVOP3(MCInst &Inst, const OperandVector &Operands) argument
[all...]
/external/llvm/utils/TableGen/
H A DFastISelEmitter.cpp118 SmallVector<OpKind, 3> Operands;
121 return Operands < O.Operands;
124 return Operands == O.Operands;
127 bool empty() const { return Operands.empty(); }
130 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
131 if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
140 for (unsigned i = 0, e = Operands
[all...]
H A DAsmWriterInst.cpp166 Operands.push_back(AsmWriterOperand("PrintSpecial",
173 unsigned OpNo = CGI.Operands.getOperandNamed(VarName);
174 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo];
177 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName,
185 Operands.push_back(AsmWriterOperand("return;",
194 if (Operands.size() != Other.Operands.size()) return ~1;
197 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
198 if (Operands[i] != Other.Operands[
[all...]
H A DAsmWriterInst.h93 std::vector<AsmWriterOperand> Operands; member in class:llvm::AsmWriterInst
108 if (!Operands.empty() &&
109 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
110 Operands.back().Str.append(Str);
112 Operands.push_back(AsmWriterOperand(Str));
H A DPseudoLoweringEmitter.cpp93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
101 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
103 OpsAdded += Insn.Operands[i].MINumOperands;
146 if (Insn.Operands.size() != Dag->getNumArgs())
151 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
152 NumMIOperands += Insn.Operands[i].MINumOperands;
160 // Operands that are a subclass of OperandWithDefaultOp have default values.
170 for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i)
171 SourceOperands[SourceInsn.Operands[
[all...]
H A DInstrInfoEmitter.cpp64 std::map<std::string, unsigned> &Operands,
91 for (auto &Op : Inst.Operands) {
196 /// \param Operands [out] A map used to generate the OpName enum with operand
204 std::map<std::string, unsigned> &Operands,
212 for (const auto &Info : Inst->Operands) {
213 StrUintMapIter I = Operands.find(Info.Name);
215 if (I == Operands.end()) {
216 I = Operands.insert(Operands.begin(),
244 std::map<std::string, unsigned> Operands; local
201 initOperandMapData( const std::vector<const CodeGenInstruction *> &NumberedInstructions, const std::string &Namespace, std::map<std::string, unsigned> &Operands, OpNameMapTy &OperandMap) argument
314 std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand"); local
[all...]
H A DCodeEmitterGen.cpp88 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
90 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
91 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
94 unsigned NumberOps = CGI.Operands.size();
98 (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
100 CGI.Operands.getSubOperandNumber(NumberedOp).first)))) {
103 if (NumberedOp >= CGI.Operands.back().MIOperandNo +
104 CGI.Operands.back().MINumOperands) {
117 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
118 std::string &EncoderMethodName = CGI.Operands[S
[all...]
H A DAsmWriterEmitter.cpp115 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
118 O << " " << FirstInst.Operands[i].getCode();
126 FirstInst.Operands[i]));
132 AWI.Operands[i]));
163 if (Inst->Operands.empty())
166 Command = " " + Inst->Operands[0].getCode() + "\n";
205 if (!FirstInst || FirstInst->Operands.size() == Op)
220 if (!OtherInst || OtherInst->Operands.size() == Op ||
221 OtherInst->Operands[Op] != FirstInst->Operands[O
[all...]
H A DFixedLenDecoderEmitter.cpp315 const std::map<unsigned, std::vector<OperandInfo> > &Operands; member in class:__anon11370::FilterChooser
345 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(),
356 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops),
553 Owner->Operands, BitValueArray, *Owner)));
580 Owner->Operands, BitValueArray, *Owner)));
1063 for (const auto &Op : Operands.find(Opc)->second) {
1667 std::map<unsigned, std::vector<OperandInfo> > &Operands){
1683 Operands[Opc] = InsnOperands;
1705 for (unsigned i = 0; i < CGI.Operands.size(); ++i) {
1706 int tiedTo = CGI.Operands[
[all...]
/external/llvm/include/llvm/MC/
H A DMCInst.h153 SmallVector<MCOperand, 8> Operands; member in class:llvm::MCInst
163 const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
164 MCOperand &getOperand(unsigned i) { return Operands[i]; }
165 unsigned getNumOperands() const { return Operands.size(); }
168 Operands.push_back(Op);
171 void clear() { Operands.clear(); }
172 size_t size() const { return Operands.size(); }
176 iterator begin() { return Operands.begin(); }
177 const_iterator begin() const { return Operands.begin(); }
178 iterator end() { return Operands
[all...]
H A DMCTargetAsmParser.h141 /// \param Operands [out] - The list of parsed operands, this returns
145 SMLoc NameLoc, OperandVector &Operands) = 0;
170 OperandVector &Operands, MCStreamer &Out,
193 const OperandVector &Operands) = 0;
/external/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp345 OperandMatchResultTy parseRegister(OperandVector &Operands,
353 OperandMatchResultTy parseAddress(OperandVector &Operands,
357 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
360 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
377 SMLoc NameLoc, OperandVector &Operands) override;
379 OperandVector &Operands, MCStreamer &Out,
384 OperandMatchResultTy parseGR32(OperandVector &Operands) { argument
385 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
387 OperandMatchResultTy parseGRH32(OperandVector &Operands) { argument
388 return parseRegister(Operands, RegG
390 parseGRX32(OperandVector &Operands) argument
393 parseGR64(OperandVector &Operands) argument
396 parseGR128(OperandVector &Operands) argument
399 parseADDR32(OperandVector &Operands) argument
402 parseADDR64(OperandVector &Operands) argument
405 parseADDR128(OperandVector &Operands) argument
408 parseFP32(OperandVector &Operands) argument
411 parseFP64(OperandVector &Operands) argument
414 parseFP128(OperandVector &Operands) argument
417 parseBDAddr32(OperandVector &Operands) argument
420 parseBDAddr64(OperandVector &Operands) argument
423 parseBDXAddr64(OperandVector &Operands) argument
426 parseBDLAddr64(OperandVector &Operands) argument
430 parsePCRel16(OperandVector &Operands) argument
433 parsePCRel32(OperandVector &Operands) argument
436 parsePCRelTLS16(OperandVector &Operands) argument
439 parsePCRelTLS32(OperandVector &Operands) argument
513 parseRegister(OperandVector &Operands, RegisterGroup Group, const unsigned *Regs, RegisterKind Kind) argument
581 parseAddress(OperandVector &Operands, const unsigned *Regs, RegisterKind RegKind, MemoryKind MemKind) argument
636 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) argument
669 parseOperand(OperandVector &Operands, StringRef Mnemonic) argument
713 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
766 parseAccessReg(OperandVector &Operands) argument
781 parsePCRel(OperandVector &Operands, int64_t MinVal, int64_t MaxVal, bool AllowTLS) argument
[all...]
/external/llvm/include/llvm/Analysis/
H A DScalarEvolutionExpressions.h140 const SCEV *const *Operands; member in class:llvm::SCEVNAryExpr
145 : SCEV(ID, T), Operands(O), NumOperands(N) {}
151 return Operands[i];
156 op_iterator op_begin() const { return Operands; }
157 op_iterator op_end() const { return Operands + NumOperands; }
298 const SCEV *getStart() const { return Operands[0]; }
671 SmallVector<const SCEV *, 2> Operands; local
673 Operands.push_back(visit(Expr->getOperand(i)));
674 return SE.getAddExpr(Operands);
678 SmallVector<const SCEV *, 2> Operands; local
689 SmallVector<const SCEV *, 2> Operands; local
697 SmallVector<const SCEV *, 2> Operands; local
704 SmallVector<const SCEV *, 2> Operands; local
767 SmallVector<const SCEV *, 2> Operands; local
774 SmallVector<const SCEV *, 2> Operands; local
785 SmallVector<const SCEV *, 2> Operands; local
800 SmallVector<const SCEV *, 2> Operands; local
807 SmallVector<const SCEV *, 2> Operands; local
[all...]
H A DConstantFolding.h98 Constant *ConstantFoldCall(Function *F, ArrayRef<Constant *> Operands,
/external/llvm/lib/Analysis/
H A DScalarEvolutionNormalization.cpp109 SmallVector<const SCEV *, 8> Operands; local
116 Operands.push_back(TransformSubExpr(*I, LUser, nullptr));
119 const SCEV *Result = SE.getAddRecExpr(Operands, L, SCEV::FlagAnyWrap);
191 SmallVector<const SCEV *, 8> Operands; local
199 Operands.push_back(N);
204 case scAddExpr: return SE.getAddExpr(Operands);
205 case scMulExpr: return SE.getMulExpr(Operands);
206 case scSMaxExpr: return SE.getSMaxExpr(Operands);
207 case scUMaxExpr: return SE.getUMaxExpr(Operands);
H A DConstantFolding.cpp1402 Type *Ty, ArrayRef<Constant *> Operands,
1404 if (Operands.size() == 1) {
1405 if (ConstantFP *Op = dyn_cast<ConstantFP>(Operands[0])) {
1537 if (ConstantInt *Op = dyn_cast<ConstantInt>(Operands[0])) {
1563 if (isa<ConstantVector>(Operands[0]) ||
1564 isa<ConstantDataVector>(Operands[0])) {
1565 Constant *Op = cast<Constant>(Operands[0]);
1587 if (isa<UndefValue>(Operands[0])) {
1589 return Operands[0];
1596 if (Operands
1401 ConstantFoldScalarCall(StringRef Name, unsigned IntrinsicID, Type *Ty, ArrayRef<Constant *> Operands, const TargetLibraryInfo *TLI) argument
1736 ConstantFoldVectorCall(StringRef Name, unsigned IntrinsicID, VectorType *VTy, ArrayRef<Constant *> Operands, const TargetLibraryInfo *TLI) argument
1767 ConstantFoldCall(Function *F, ArrayRef<Constant *> Operands, const TargetLibraryInfo *TLI) argument
[all...]
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp57 bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
59 bool parseCondCode(OperandVector &Operands, bool invertCondCode);
63 bool parseRegister(OperandVector &Operands);
65 bool parseVectorList(OperandVector &Operands);
66 bool parseOperand(OperandVector &Operands, bool isCondCode,
86 OperandVector &Operands, MCStreamer &Out,
97 OperandMatchResultTy tryParseOptionalShiftExtend(OperandVector &Operands);
98 OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
99 OperandMatchResultTy tryParseMRSSystemRegister(OperandVector &Operands);
100 OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
1919 tryParseSysCROperand(OperandVector &Operands) argument
1949 tryParsePrefetch(OperandVector &Operands) argument
2005 tryParseAdrpLabel(OperandVector &Operands) argument
2056 tryParseAdrLabel(OperandVector &Operands) argument
2076 tryParseFPImm(OperandVector &Operands) argument
2140 tryParseAddSubImm(OperandVector &Operands) argument
2231 parseCondCode(OperandVector &Operands, bool invertCondCode) argument
2258 tryParseOptionalShiftExtend(OperandVector &Operands) argument
2331 parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands) argument
2578 tryParseBarrierOperand(OperandVector &Operands) argument
2638 tryParseSysReg(OperandVector &Operands) argument
2672 tryParseVectorRegister(OperandVector &Operands) argument
2721 parseRegister(OperandVector &Operands) argument
2843 parseVectorList(OperandVector &Operands) argument
2942 tryParseGPR64sp0Operand(OperandVector &Operands) argument
2987 parseOperand(OperandVector &Operands, bool isCondCode, bool invertCondCode) argument
3152 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) argument
3606 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
[all...]
/external/llvm/lib/IR/
H A DConstantsContext.h342 ArrayRef<Constant *> Operands; member in struct:llvm::ConstantAggrKeyType
343 ConstantAggrKeyType(ArrayRef<Constant *> Operands) : Operands(Operands) {} argument
344 ConstantAggrKeyType(ArrayRef<Constant *> Operands, const ConstantClass *) argument
345 : Operands(Operands) {}
351 Operands = Storage;
355 return Operands == X.Operands;
430 ConstantExprKeyType(ArrayRef<Constant *> Operands, const ConstantExpr *CE) argument
604 replaceOperandsInPlace(ArrayRef<Constant *> Operands, ConstantClass *CP, Value *From, Constant *To, unsigned NumUpdated = 0, unsigned OperandNo = ~0u) argument
[all...]
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp192 bool validatetLDMRegList(MCInst Inst, const OperandVector &Operands,
194 bool validatetSTMRegList(MCInst Inst, const OperandVector &Operands,
334 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
335 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
368 SMLoc NameLoc, OperandVector &Operands) override;
376 OperandVector &Operands, MCStreamer &Out,
3048 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { argument
3074 (ARMOperand *)Operands.pop_back_val().release());
3134 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3138 Operands
3151 tryParseRegisterWithWriteBack(OperandVector &Operands) argument
3248 parseITCondCode(OperandVector &Operands) argument
3286 parseCoprocNumOperand(OperandVector &Operands) argument
3309 parseCoprocRegOperand(OperandVector &Operands) argument
3328 parseCoprocOptionOperand(OperandVector &Operands) argument
3406 parseRegisterList(OperandVector &Operands) argument
3590 parseVectorList(OperandVector &Operands) argument
3842 parseMemBarrierOptOperand(OperandVector &Operands) argument
3914 parseInstSyncBarrierOptOperand(OperandVector &Operands) argument
3966 parseProcIFlagsOperand(OperandVector &Operands) argument
4001 parseMSRMaskOperand(OperandVector &Operands) argument
4134 parseBankedRegOperand(OperandVector &Operands) argument
4189 parsePKHImm(OperandVector &Operands, StringRef Op, int Low, int High) argument
4238 parseSetEndImm(OperandVector &Operands) argument
4268 parseShifterImm(OperandVector &Operands) argument
4339 parseRotImm(OperandVector &Operands) argument
4386 parseModImm(OperandVector &Operands) argument
4503 parseBitfield(OperandVector &Operands) argument
4572 parsePostIdxReg(OperandVector &Operands) argument
4622 parseAM3Offset(OperandVector &Operands) argument
4695 cvtThumbMultiply(MCInst &Inst, const OperandVector &Operands) argument
4711 cvtThumbBranches(MCInst &Inst, const OperandVector &Operands) argument
4771 parseMemory(OperandVector &Operands) argument
5024 parseFPImm(OperandVector &Operands) argument
5105 parseOperand(OperandVector &Operands, StringRef Mnemonic) argument
5468 shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands) argument
5591 shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands) argument
5649 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) argument
6023 validatetLDMRegList(MCInst Inst, const OperandVector &Operands, unsigned ListNo, bool IsARPop) argument
6046 validatetSTMRegList(MCInst Inst, const OperandVector &Operands, unsigned ListNo) argument
6068 validateInstruction(MCInst &Inst, const OperandVector &Operands) argument
6694 processInstruction(MCInst &Inst, const OperandVector &Operands, MCStreamer &Out) argument
8577 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
9532 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; local
[all...]
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp694 void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
697 OperandVector &Operands, MCStreamer &Out,
701 void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
708 OperandVector &Operands, MCStreamer &Out,
713 OperandVector &Operands, MCStreamer &Out,
725 /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
727 bool HandleAVX512Operand(OperandVector &Operands,
786 SMLoc NameLoc, OperandVector &Operands) override;
1756 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands, argument
1790 Operands
1997 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) argument
2459 EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out) argument
2465 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
2476 MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands, MCStreamer &Out, bool MatchingInlineAsm) argument
2518 MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
2693 MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
[all...]
H A DX86AsmInstrumentation.h45 SmallVectorImpl<std::unique_ptr<MCParsedAsmOperand> > &Operands,
/external/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp50 OperandVector &Operands, MCStreamer &Out,
55 SMLoc NameLoc, OperandVector &Operands) override;
62 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
64 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
70 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
387 OperandVector &Operands,
393 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
409 if (ErrorInfo >= Operands.size())
412 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
449 OperandVector &Operands) {
386 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
447 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) argument
544 parseMEMOperand(OperandVector &Operands) argument
582 parseOperand(OperandVector &Operands, StringRef Mnemonic) argument
710 parseBranchModifiers(OperandVector &Operands) argument
[all...]
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp124 OperandVector &Operands, MCStreamer &Out,
131 bool parseParenSuffix(StringRef Name, OperandVector &Operands);
133 bool parseBracketSuffix(StringRef Name, OperandVector &Operands);
136 SMLoc NameLoc, OperandVector &Operands) override;
140 MipsAsmParser::OperandMatchResultTy parseMemOperand(OperandVector &Operands);
143 matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
147 matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S);
149 MipsAsmParser::OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
151 MipsAsmParser::OperandMatchResultTy parseImm(OperandVector &Operands);
153 MipsAsmParser::OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
2162 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) argument
2417 parseOperand(OperandVector &Operands, StringRef Mnemonic) argument
2618 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; local
2672 parseMemOperand(OperandVector &Operands) argument
2755 searchSymbolAlias(OperandVector &Operands) argument
2790 matchAnyRegisterNameWithoutDollar(OperandVector &Operands, StringRef Identifier, SMLoc S) argument
2846 matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) argument
2870 parseAnyRegister(OperandVector &Operands) argument
2898 parseImm(OperandVector &Operands) argument
2923 parseJumpTarget(OperandVector &Operands) argument
2950 parseInvNum(OperandVector &Operands) argument
2969 parseLSAImm(OperandVector &Operands) argument
3009 parseRegisterList(OperandVector &Operands) argument
3085 parseRegisterPair(OperandVector &Operands) argument
3101 parseMovePRegPair(OperandVector &Operands) argument
3180 parseParenSuffix(StringRef Name, OperandVector &Operands) argument
3209 parseBracketSuffix(StringRef Name, OperandVector &Operands) argument
3233 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) argument
[all...]
/external/llvm/lib/Transforms/IPO/
H A DArgumentPromotion.cpp471 IndicesVector Operands; local
474 Operands.clear();
480 Operands.push_back(0);
497 Operands.push_back(C->getSExtValue());
516 // is safe if Operands, or a prefix of Operands, is marked as safe.
517 if (!PrefixIn(Operands, SafeToUnconditionallyLoad))
523 if (ToPromote.find(Operands) == ToPromote.end()) {
532 ToPromote.insert(std::move(Operands));
956 IndicesVector Operands; local
[all...]
/external/llvm/test/MC/X86/
H A Dx86_operands.s30 # Indirect Memory Operands

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