| /external/llvm/test/MC/Mips/ |
| H A D | mips-reginfo-fp32.s | 25 # abs.s - Reads and writes from/to $f0.
27 # round.w.d - Reads $f4 and $f5 and writes to $f2.
29 # ceil.w.s - Reads $f8 and writes to $f10.
31 # cvt.s.d - Reads from $f12 and $f13 and writes to $f14
33 # abs.d - Reads from $f30 and $f31 and writes to $f30 and $f31.
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| H A D | mips-reginfo-fp64.s | 47 # abs.s - Reads and writes from/to $f0.
49 # round.w.d - Reads $f4 and writes to $f2.
51 # ceil.w.s - Reads $f8 and writes to $f10.
53 # cvt.s.d - Reads from $f12 and writes to $f14.
55 # abs.d - Reads from $f30 and writes to $f30.
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| /external/llvm/utils/TableGen/ |
| H A D | CodeGenSchedule.h | 70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
126 /// that mapped the itinerary class to the variant Writes or Reads.
133 IdxVec Reads; member in struct:llvm::CodeGenSchedClass
148 return ItinClassDef == IC && Writes == W && Reads == R;
360 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
373 const IdxVec &Reads) const;
418 void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
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| H A D | CodeGenSchedule.cpp | 187 // Reads don't current have sequence records, but it can be added later.
386 IdxVec &Writes, IdxVec &Reads) const {
391 findRWs(ReadDefs, Reads, true);
512 IdxVec Writes, Reads;
514 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
519 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
558 for (IdxIter RI = SC.Reads.begin(), RE = SC.Reads.end(); RI != RE; ++RI)
570 IdxVec Reads;
572 Writes, Reads);
[all...] |
| H A D | SubtargetEmitter.cpp | 871 IdxVec Reads = SCI->Reads; local
886 Reads.clear();
888 Writes, Reads);
899 Writes, Reads);
980 for (unsigned UseIdx = 0, EndIdx = Reads.size();
983 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBundle.h | 154 /// Reads - One of the operands read the virtual register. This does not
156 bool Reads; member in struct:llvm::MachineOperandIteratorBase::VirtRegInfo
177 /// Reads - Read or a super-register is read.
178 bool Reads; member in struct:llvm::MachineOperandIteratorBase::PhysRegInfo
|
| /external/llvm/lib/CodeGen/ |
| H A D | EarlyIfConversion.cpp | 274 SmallVector<unsigned, 8> Reads; local
300 Reads.push_back(Reg);
303 while (!Reads.empty())
304 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
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| H A D | MachineInstrBundle.cpp | 267 RI.Reads = true;
307 PRI.Reads = true;
|
| H A D | RegisterCoalescer.cpp | 1146 bool Reads, Writes; local
1147 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
1151 if (DstInt && !Reads && SubIdx)
1152 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
1162 MO.setIsUndef(!Reads);
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| H A D | InlineSpiller.cpp | 864 if (!RI.Reads)
1298 if (RI.Reads)
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| H A D | MachineBasicBlock.cpp | 1159 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1188 return (Analysis.Reads) ?
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| /external/blktrace/doc/ |
| H A D | blktrace.tex | 163 Reads Queued: 0, 0KiB Writes Queued: 7, 128KiB
165 Reads Completed: 0, 0KiB Writes Completed: 11, 168KiB
170 Reads Queued: 0, 0KiB Writes Queued: 1, 28KiB
172 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
177 Reads Queued: 0, 0KiB Writes Queued: 11, 168KiB
179 Reads Completed: 0, 0KiB Writes Completed: 11, 168KiB
299 Reads Queued: 0, 0KiB Writes Queued: 9, 5,520KiB
301 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
305 Reads Queued: 2,411, 38,576KiB Writes Queued: 769, 425,408KiB
307 Reads Complete
[all...] |
| /external/libvpx/libvpx/build/make/ |
| H A D | rtcd.pl | 412 Reads the Run Time CPU Detections definitions from FILE and generates a
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ConditionalCompares.cpp | 356 if (PRI.Reads) {
|