Searched refs:Rm (Results 1 - 25 of 27) sorted by relevance

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/external/vogar/src/vogar/tasks/
H A DRmTask.java21 import vogar.commands.Rm;
24 private final Rm rm;
27 public RmTask(Rm rm, File file) {
/external/vogar/src/vogar/commands/
H A DRm.java25 public final class Rm { class
28 public Rm(Log log) { method in class:Rm
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1144 unsigned Rm = fieldFromInstruction(Val, 0, 4); local
1149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1181 unsigned Rm = fieldFromInstruction(Val, 0, 4); local
1186 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1481 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
1543 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1585 unsigned Rm = fieldFromInstruction(Val, 0, 4); local
1611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1630 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
1663 if (type && Rm
1849 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2104 unsigned Rm = fieldFromInstruction(Insn, 8, 4); local
2132 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2276 unsigned Rm = fieldFromInstruction(Val, 0, 4); local
2298 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2623 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2892 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2939 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
2987 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3022 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3119 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3164 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3245 unsigned Rm = fieldFromInstruction(Val, 3, 3); local
3292 unsigned Rm = fieldFromInstruction(Val, 2, 4); local
3864 unsigned Rm = fieldFromInstruction(Insn, 3, 4); local
3889 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
3943 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4243 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4316 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4383 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4449 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4516 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4580 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4650 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4714 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4795 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local
4867 unsigned Rm = fieldFromInstruction(Insn, 5, 1); local
4893 unsigned Rm = fieldFromInstruction(Insn, 5, 1); local
5124 unsigned Rm = fieldFromInstruction(Val, 0, 4); local
[all...]
/external/v8/src/arm64/
H A Ddisasm-arm64.h59 return (instr->Rm() == kZeroRegCode);
H A Dsimulator-arm64.cc875 T op2 = reg<T>(instr->Rm());
954 T op2 = reg<T>(instr->Rm());
1398 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount);
1401 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount);
1421 int64_t op2 = ExtendValue(xreg(instr->Rm()), ext, left_shift);
1424 int32_t op2 = ExtendValue(wreg(instr->Rm()), ext, left_shift);
1444 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount);
1448 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount);
1495 ConditionalCompareHelper(instr, xreg(instr->Rm()));
1497 ConditionalCompareHelper(instr, wreg(instr->Rm()));
[all...]
H A Dassembler-arm64.cc1245 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
1254 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
1263 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
1272 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
1323 Emit(SF(rd) | EXTR | N | Rm(rm) |
1399 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
1424 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
1526 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
1535 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
1949 Emit(FPType(fn) | FCMP | Rm(f
[all...]
H A Dinstructions-arm64.h334 (Rd() == Rm()) &&
H A Ddisasm-arm64.cc101 const char *form = "'Rd, 'Rn, 'Rm'HDP";
102 const char *form_cmp = "'Rn, 'Rm'HDP";
103 const char *form_neg = "'Rd, 'Rm'HDP";
185 const char *form = "'Rd, 'Rn, 'Rm";
186 const char *form_neg = "'Rd, 'Rm";
293 const char *form = "'Rd, 'Rn, 'Rm'HLo";
311 form = "'Rn, 'Rm'HLo";
320 form = "'Rd, 'Rm";
329 form = "'Rd, 'Rm'HLo";
342 const char *form = "'Rn, 'Rm, 'INzc
[all...]
H A Dconstants-arm64.h127 V_(Rm, 20, 16, Bits) /* Second source register. */ \
H A Dassembler-arm64.h1772 static Instr Rm(CPURegister rm) {
/external/vogar/src/vogar/
H A DOutcomeStore.java34 import vogar.commands.Rm;
51 private final Rm rm;
57 public OutcomeStore(Log log, Mkdir mkdir, Rm rm, File resultsDir, boolean recordResults,
H A DRun.java36 import vogar.commands.Rm;
61 public final Rm rm;
134 this.rm = new Rm(console);
/external/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp739 uint32_t Rm; // the source register local
745 Rm = Bits32(opcode, 6, 3);
752 Rm = Bits32(opcode, 5, 3);
759 Rm = Bits32(opcode, 3, 0);
762 if (setflags && (BadReg(Rd) || BadReg(Rm)))
765 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
770 Rm = Bits32(opcode, 3, 0);
780 uint32_t result = ReadCoreReg(Rm, &success);
784 // The context specifies that Rm i
1124 uint32_t Rm; // the source register local
1600 uint32_t Rm; // the register with the target address local
1654 uint32_t Rm; // the register with the target address local
2392 uint32_t Rm; // the index register which contains an integer pointing to a byte/halfword in the table local
2642 uint32_t Rd, Rn, Rm; local
2777 uint32_t Rm; // the second operand local
2901 uint32_t Rm; // the second operand local
3190 uint32_t Rm; // the first operand register local
3280 uint32_t Rm; // the register whose bottom byte contains the amount to shift by local
5156 uint32_t Rm = ReadCoreReg (m, &success); local
5325 uint32_t Rd, Rn, Rm; local
5550 uint32_t Rd, Rn, Rm; local
5713 uint32_t Rd, Rn, Rm; local
6033 uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local
6448 uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local
6864 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local
7270 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local
7699 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local
7830 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local
7914 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local
7998 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local
8079 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local
8350 uint32_t Rd, Rn, Rm; local
8516 uint32_t Rd, Rn, Rm; local
8679 uint32_t Rm; // the second operand local
8818 uint32_t Rm; // the second operand local
8955 uint32_t Rm; // the second operand local
9249 uint32_t Rn, Rm; local
9373 uint32_t Rn, Rm; local
9495 uint32_t Rm = ReadCoreReg (m, &success); local
9584 uint32_t Rm = ReadCoreReg (m, &success); local
9709 uint32_t Rm = ReadCoreReg (m, &success); local
10280 uint32_t Rm = ReadCoreReg (m, &success); local
11392 uint32_t Rm = ReadCoreReg (m, &success); local
11564 uint32_t Rm = ReadCoreReg (m, &success); local
11731 uint32_t Rm = ReadCoreReg (m, &success); local
11903 uint32_t Rm = ReadCoreReg (m, &success); local
12029 uint32_t Rm = ReadCoreReg (m, &success); local
12154 uint32_t Rm = ReadCoreReg (m, &success); local
[all...]
/external/v8/src/arm/
H A Ddisasm-arm.cc91 void FormatNeonMemory(int Rn, int align, int Rm);
315 } else if (format[1] == 'm') { // 'rm: Rm register
416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { argument
423 if (Rm == 15) {
425 } else if (Rm == 13) {
429 "], r%d", Rm);
717 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
723 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
735 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs>
1577 int Rm local
1590 int Rm = instr->VmValue(); local
[all...]
H A Dsimulator-arm.cc2031 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
3503 int Rm = instr->VmValue(); local
3532 if (Rm != 15) {
3533 if (Rm == 13) {
3536 set_register(Rn, get_register(Rn) + get_register(Rm));
3544 int Rm = instr->VmValue(); local
3573 if (Rm != 15) {
3574 if (Rm == 13) {
3577 set_register(Rn, get_register(Rn) + get_register(Rm));
/external/vixl/examples/
H A Dnon-const-visitor.h42 int rm = instr->Rm();
/external/vixl/src/vixl/a64/
H A Ddisasm-a64.h137 return (instr->Rm() == kZeroRegCode);
H A Dsimulator-a64.cc939 reg(reg_size, instr->Rm()),
955 reg(reg_size, instr->Rm()),
964 int64_t op2 = reg(reg_size, instr->Rm());
985 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type,
1030 ConditionalCompareHelper(instr, reg(reg_size, instr->Rm()));
1087 int64_t offset = ExtendValue(kXRegSize, xreg(instr->Rm()), ext,
1587 new_val = xreg(instr->Rm());
1710 int32_t rm = wreg(instr->Rm());
1723 int64_t rm = xreg(instr->Rm());
1736 uint32_t rm = static_cast<uint32_t>(wreg(instr->Rm()));
[all...]
H A Dassembler-a64.cc701 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd));
1023 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
1032 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
1041 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
1050 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
1095 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.size()) | Rn(rn) | Rd(rd));
1170 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
1195 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
1203 Emit(SF(rm) | Rm(rm) | CRC32B | Rn(rn) | Rd(rd));
1211 Emit(SF(rm) | Rm(r
[all...]
H A Ddisasm-a64.cc111 const char *form = "'Rd, 'Rn, 'Rm'NDP";
112 const char *form_cmp = "'Rn, 'Rm'NDP";
113 const char *form_neg = "'Rd, 'Rm'NDP";
195 const char *form = "'Rd, 'Rn, 'Rm";
196 const char *form_neg = "'Rd, 'Rm";
303 const char *form = "'Rd, 'Rn, 'Rm'NLo";
321 form = "'Rn, 'Rm'NLo";
330 form = "'Rd, 'Rm";
339 form = "'Rd, 'Rm'NLo";
352 const char *form = "'Rn, 'Rm, 'INzc
[all...]
H A Dassembler-a64.h3694 static Instr Rm(CPURegister rm) {
3702 return Rm(rm);
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp737 unsigned Rm = fieldFromInstruction(insn, 16, 5); local
765 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
786 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1290 unsigned Rm = fieldFromInstruction(insn, 16, 5); local
1304 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1310 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1316 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1322 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1328 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1334 DecodeGPR64RegisterClass(Inst, Rm, Add
[all...]
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp2770 unsigned Rm = MI->getOperand(3).getReg(); local
2771 return (Rt == Rm) ? 4 : 3;
2777 unsigned Rm = MI->getOperand(3).getReg(); local
2778 if (Rt == Rm)
2807 unsigned Rm = MI->getOperand(3).getReg(); local
2808 if (!Rm)
2810 if (Rt == Rm)
2820 unsigned Rm = MI->getOperand(3).getReg(); local
2821 return (Rt == Rm) ? 3 : 2;
2839 unsigned Rm local
2859 unsigned Rm = MI->getOperand(3).getReg(); local
2866 unsigned Rm = MI->getOperand(3).getReg(); local
2883 unsigned Rm = MI->getOperand(4).getReg(); local
2896 unsigned Rm = MI->getOperand(4).getReg(); local
[all...]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp868 // [Rn, Rm]
869 // {5-3} = Rm
874 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); local
875 return (Rm << 3) | Rn;
1081 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); local
1094 // {3-0} = Rm
1098 uint32_t Binary = Rm;
1112 // {13} 1 == imm12, 0 == Rm
1114 // {11-0} imm12/Rm
1126 // {13} 1 == imm12, 0 == Rm
[all...]
/external/valgrind/none/tests/arm/
H A Dvfp.stdout.exp922 vstr d9, [r6, #+4] :: Dd 0xa0a0a0a0 0xa0a0a0a0 *(int*) (Rm + shift) 0xa0a0a0a0
923 vstr d16, [r9, #-4] :: Dd 0xb1b1b1b1 0xb1b1b1b1 *(int*) (Rm + shift) 0xb1b1b1b1
924 vstr d30, [r12] :: Dd 0xc2c2c2c2 0xc2c2c2c2 *(int*) (Rm + shift) 0xc2c2c2c2
925 vstr d22, [r9, #+8] :: Dd 0xd4d4d4d4 0xd4d4d4d4 *(int*) (Rm + shift) 0xd4d4d4d4
926 vstr d29, [r2, #-8] :: Dd 0x00000000 0x00000000 *(int*) (Rm + shift) 0x0000
927 vstr d8, [r8, #+8] :: Dd 0x11111111 0x11111111 *(int*) (Rm + shift) 0x11111111
928 vstr d11, [r12, #-4] :: Dd 0x22222222 0x22222222 *(int*) (Rm + shift) 0x22222222
929 vstr d18, [r3] :: Dd 0x33333333 0x33333333 *(int*) (Rm + shift) 0x33333333
930 vstr d5, [r10, #+8] :: Dd 0x99999999 0x99999999 *(int*) (Rm + shift) 0x99999999
931 vstr d17, [r10] :: Dd 0x77777777 0x77777777 *(int*) (Rm
[all...]

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