Searched refs:Src1Reg (Results 1 - 6 of 6) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 278 unsigned Src1Reg = MI->getOperand(2).getReg(); local
294 .addReg(Src1Reg, getKillRegState(Src1Kill))
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| /external/llvm/lib/Target/R600/ |
| H A D | R600InstrInfo.h | 244 unsigned Src1Reg = 0) const;
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| H A D | R600InstrInfo.cpp | 1186 unsigned Src1Reg) const {
1190 if (Src1Reg) {
1204 if (Src1Reg) {
1205 MIB.addReg(Src1Reg) // $src1
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| H A D | SIInstrInfo.cpp | 953 unsigned Src1Reg = Src1->getReg(); local
957 Src0->setReg(Src1Reg);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 595 unsigned Src1Reg = MI->getOperand(1).getReg(); local
597 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
598 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
617 unsigned Src1Reg = MI->getOperand(1).getReg(); local
620 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
621 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2562 unsigned Src1Reg = getRegForValue(Src1Val); local
2563 if (!Src1Reg)
2573 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1);
2576 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32spRegClass, Src1Reg,
2689 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); local
2695 if (!Src1Reg || !Src2Reg)
2699 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
2703 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
4468 unsigned Src1Reg local
4546 unsigned Src1Reg = getRegForValue(I->getOperand(1)); local
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