Searched refs:dw5 (Results 1 - 4 of 4) sorted by relevance
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | gen6_wm_state.c | 99 uint32_t dw2, dw4, dw5, dw6; local 131 dw2 = dw4 = dw5 = dw6 = 0; 133 dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0; 134 dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5; 151 dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT; 155 dw5 |= GEN6_WM_8_DISPATCH_ENABLE; 157 dw5 |= GEN6_WM_16_DISPATCH_ENABLE; 159 dw5 |= GEN6_WM_16_DISPATCH_ENABLE; 166 dw5 |= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE; 171 dw5 | [all...] |
H A D | gen7_wm_state.c | 117 uint32_t dw2, dw4, dw5; local 162 dw2 = dw4 = dw5 = 0; 207 dw5 |= (brw->wm.prog_data->first_curbe_grf << 209 dw5 |= (brw->wm.prog_data->first_curbe_grf_16 << 224 OUT_BATCH(dw5);
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H A D | gen6_blorp.cpp | 52 * (dw5 of 3DSTATE_DEPTH_BUFFER). See the emit_depthbuffer() function for 180 * dw5: Vertex Position Y. 712 uint32_t dw2, dw4, dw5, dw6; local 714 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be 723 dw2 = dw4 = dw5 = dw6 = 0; 741 dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0; 742 dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5; 743 dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT; 749 dw5 |= GEN6_WM_16_DISPATCH_ENABLE; 750 dw5 | [all...] |
H A D | gen7_blorp.cpp | 410 * Disable thread dispatch (dw5.19) and enable the HiZ op. 483 uint32_t dw2, dw4, dw5; local 487 dw2 = dw4 = dw5 = 0; 503 dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0; 512 OUT_BATCH(dw5); 597 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
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