| /external/compiler-rt/lib/builtins/ppc/ |
| H A D | restFP.S | 30 lfd f21,-88(r1)
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| H A D | saveFP.S | 28 stfd f21,-88(r1)
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| /external/compiler-rt/test/cfi/ |
| H A D | utils.h | 36 virtual void f21() {} function in class:Deriver
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| /external/llvm/test/MC/ARM/ |
| H A D | symbol-variants.s | 71 .word f21(tlsldo)
73 @CHECK: 54 R_ARM_TLS_LDO32 f21
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| /external/clang/test/CodeGenCXX/ |
| H A D | aarch64-mangle-neon-vectors.cpp | 80 void f21(int64x2_t) {} function
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| H A D | debug-info-line.cpp | 256 void f21() { function
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| /external/clang/test/CodeGen/ |
| H A D | arm-arguments.c | 119 // APCS-GNU-LABEL: define i8 @f21()
120 // AAPCS-LABEL: define arm_aapcscc i32 @f21()
122 struct s21 f21(void) {} function
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| H A D | x86_32-arguments-darwin.c | 99 // CHECK: void @f21(%{{.*}}* noalias sret %agg.result)
105 struct { T15 a; } f21(void) { while (1) {} } function
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| H A D | x86_64-arguments.c | 122 // CHECK-LABEL: define i8* @f21(i64 %S.coerce0, i8* %S.coerce1)
123 const char *f21(struct StringRef S) { return S.x+S.Ptr; } function
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| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips5-wrong-error.s | 17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
20 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips5-wrong-error.s | 17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
20 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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| /external/llvm/test/MC/Mips/mips3/ |
| H A D | invalid-mips5-wrong-error.s | 17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
20 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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| H A D | invalid-mips4.s | 19 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips5.s | 20 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips5-wrong-error.s | 17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
20 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips5-wrong-error.s | 20 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
23 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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| /external/v8/test/mjsunit/harmony/ |
| H A D | block-let-crankshaft.js | 34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26,
142 function f21(x) { function
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| /external/llvm/test/MC/ELF/ |
| H A D | cfi.s | 125 f21: label
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| /external/llvm/test/MC/PowerPC/ |
| H A D | ppc64-regs.s | 60 #CHECK: .cfi_offset f21, 468
177 .cfi_offset f21,468
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| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips32.s | 18 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/clang/test/Analysis/ |
| H A D | dead-stores.c | 229 int f21() { function
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| /external/libunwind/src/ia64/ |
| H A D | getcontext.S | 151 stf.spill [r9] = f21, (FR(23) - FR(21)) // M3
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| /external/mesa3d/src/mesa/sparc/ |
| H A D | sparc_matrix.h | 40 #define M5 %f21
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| /external/valgrind/none/tests/mips32/ |
| H A D | MoveIns.c | 304 TESTINSNMOVE("mfc1 $v0, $f21", 16, f21, v0);
333 TESTINSNMOVEt("mtc1 $v0, $f21", 18, f21, v0);
362 TESTINSNMOVE1s("mov.s $f20, $f21", 16, f20, f21);
363 TESTINSNMOVE1s("mov.s $f21, $f22", 20, f21, f22);
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| /external/clang/test/Misc/ |
| H A D | diag-template-diffing.cpp | 557 int f21(vector<const U21<int>>);
558 int k21 = f21(vector<U21<int>>());
559 // CHECK-ELIDE-NOTREE: no matching function for call to 'f21'
561 // CHECK-NOELIDE-NOTREE: no matching function for call to 'f21'
563 // CHECK-ELIDE-TREE: no matching function for call to 'f21'
568 // CHECK-NOELIDE-TREE: no matching function for call to 'f21'
|