| /external/compiler-rt/lib/builtins/ppc/ |
| H A D | restFP.S | 32 lfd f23,-72(r1)
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| H A D | saveFP.S | 30 stfd f23,-72(r1)
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| /external/compiler-rt/test/cfi/ |
| H A D | utils.h | 38 virtual void f23() {} function in class:Deriver
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| /external/llvm/test/MC/ARM/ |
| H A D | symbol-variants.s | 77 .word f23(tlscall)
79 @ CHECK: 5c R_ARM_TLS_CALL f23
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| /external/clang/test/CodeGenCXX/ |
| H A D | aarch64-mangle-neon-vectors.cpp | 84 void f23(float64x2_t) {} function
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| H A D | debug-info-line.cpp | 282 void f23() { function
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| /external/llvm/test/MC/Mips/mips3/ |
| H A D | invalid-mips4.s | 16 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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| H A D | invalid-mips5.s | 17 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/clang/test/CodeGen/ |
| H A D | arm-arguments.c | 125 // APCS-GNU-LABEL: define i32 @f23()
131 // AAPCS-LABEL: define arm_aapcscc i32 @f23()
137 _Complex short f23(void) {} function
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| H A D | x86_32-arguments-darwin.c | 110 // CHECK: float @f23()
113 struct { float a; } f23(void) { while (1) {} } function
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| H A D | x86_64-arguments.c | 142 void f23(int A, struct f23S B) { function
143 // CHECK-LABEL: define void @f23(i32 %A, i64 %B.coerce0, i32 %B.coerce1)
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| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips4.s | 55 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
56 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
71 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips5.s | 54 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
55 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
69 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips32.s | 26 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
27 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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| H A D | invalid-mips3.s | 52 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips32r2.s | 35 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
36 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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| /external/v8/test/mjsunit/harmony/ |
| H A D | block-let-crankshaft.js | 34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26,
153 function f23() { function
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| /external/llvm/test/MC/ELF/ |
| H A D | cfi.s | 137 f23: label
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| /external/llvm/test/MC/PowerPC/ |
| H A D | ppc64-regs.s | 63 #CHECK: .cfi_offset f23, 492
180 .cfi_offset f23,492
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| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips4.s | 59 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
60 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
86 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips5.s | 58 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
59 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
84 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips3.s | 66 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips32.s | 16 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/clang/test/Analysis/ |
| H A D | dead-stores.c | 394 void f23(int argc, char **argv) { function
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| /external/libunwind/src/ia64/ |
| H A D | getcontext.S | 158 stf.spill [r9] = f23, (FR(26) - FR(23)) // M2
|