| /external/compiler-rt/lib/builtins/ppc/ |
| H A D | restFP.S | 35 lfd f26,-48(r1)
|
| H A D | saveFP.S | 33 stfd f26,-48(r1)
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips5-wrong-error.s | 16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
27 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
46 sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| H A D | valid.s | 34 cvt.d.w $f26,$f11
35 cvt.s.d $f26,$f8
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips5-wrong-error.s | 16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
27 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
46 sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | invalid-mips5-wrong-error.s | 16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
27 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
46 sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips5-wrong-error.s | 16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
27 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
46 sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| H A D | valid.s | 56 cvt.d.w $f26,$f11
59 cvt.s.d $f26,$f8
112 floor.l.d $f26,$f7
142 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips5-wrong-error.s | 19 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
30 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
45 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
46 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
48 sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/compiler-rt/test/cfi/ |
| H A D | utils.h | 41 virtual void f26() {} function in class:Deriver
|
| /external/llvm/test/MC/ARM/ |
| H A D | symbol-variants.s | 88 .word f26(GOT_PREL) + (. - .Lsym)
90 @ CHECK: 68 R_ARM_GOT_PREL f26
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips32r2.s | 8 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/clang/test/CodeGen/ |
| H A D | arm-arguments.c | 128 // APCS-GNU-LABEL: define i64 @f26()
134 // AAPCS: define arm_aapcscc void @f26({{.*}} noalias sret
140 _Complex float f26(void) {} function
|
| H A D | x86_32-arguments-darwin.c | 118 // CHECK: i32 @f26()
120 struct s26 { struct { char a, b; } a; struct { char a, b; } b; } f26(void) { while (1) {} } function
|
| H A D | x86_64-arguments.c | 172 struct foo26 f26(struct foo26 *P) { function
173 // CHECK: define { i32*, float* } @f26(%struct.foo26* %P)
|
| /external/llvm/test/MC/Mips/ |
| H A D | mips-reginfo-fp64.s | 58 # Read and write from/to $f26 and $f27
|
| /external/v8/test/mjsunit/harmony/ |
| H A D | block-let-crankshaft.js | 34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26,
186 function f26() { function
|
| /external/llvm/test/MC/ELF/ |
| H A D | cfi.s | 155 f26: label
|
| /external/llvm/test/MC/PowerPC/ |
| H A D | ppc64-regs.s | 66 #CHECK: .cfi_offset f26, 516
183 .cfi_offset f26,516
|
| /external/valgrind/none/tests/mips32/ |
| H A D | MoveIns.c | 309 TESTINSNMOVE("mfc1 $t2, $f26", 36, f26, t2);
338 TESTINSNMOVEt("mtc1 $t2, $f26", 38, f26, t2);
367 TESTINSNMOVE1s("mov.s $f25, $f26", 36, f25, f26);
395 TESTINSNMOVE1d("mov.d $f24, $f26", 56, f24, f26);
396 TESTINSNMOVE1d("mov.d $f24, $f26", 64, f24, f26);
[all...] |
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips32r2.s | 17 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/libunwind/src/ia64/ |
| H A D | getcontext.S | 161 stf.spill [r9] = f26, (FR(28) - FR(26)) // M2
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 56 cvt.d.w $f26,$f11
59 cvt.s.d $f26,$f8
112 floor.l.d $f26,$f7
143 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 58 cvt.d.w $f26,$f11
61 cvt.s.d $f26,$f8
117 floor.l.d $f26,$f7
152 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
|
| /external/mesa3d/src/mesa/sparc/ |
| H A D | sparc_matrix.h | 45 #define M10 %f26
|