/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInstrInfo.cpp | 25 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 32 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 36 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, function in class:llvm::HexagonMCInstrInfo 51 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 66 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 80 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 94 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 102 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; 108 return (!HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() && 154 uint64_t const F = HexagonMCInstrInfo::getDesc(MCI [all...] |
H A D | HexagonMCCodeEmitter.cpp | 59 assert(HexagonMCInstrInfo::getDesc(MCII, MI).getSize() == 4 &&
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H A D | HexagonMCInstrInfo.h | 35 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); 43 const MCInstrDesc &MCID = MI->getDesc(); 46 const MCInstrDesc &LastMCID = LastMI->getDesc();
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/external/skia/debugger/QT/ |
H A D | SkGLWidget.h | 54 GrBackendRenderTargetDesc getDesc(int w, int h);
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H A D | SkGLWidget.cpp | 61 GrBackendRenderTargetDesc desc = this->getDesc(this->width(), this->height()); 85 GrBackendRenderTargetDesc SkGLWidget::getDesc(int w, int h) { function in class:SkGLWidget
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/external/llvm/lib/Support/ |
H A D | Statistic.cpp | 119 return std::strcmp(LHS->getDesc(), RHS->getDesc()) < 0; 132 Stats.Stats[i]->getDesc());
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc();
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/external/skia/src/gpu/gl/ |
H A D | GrGLGpuProgramCache.cpp | 35 return GrProgramDesc::Less(desc, entry->fProgram->getDesc()); 40 return GrProgramDesc::Less(entry->fProgram->getDesc(), desc); 107 if (hashedEntry && hashedEntry->fProgram->getDesc() == *args.fDesc) { 146 int purgedHashIdx = entry->fProgram->getDesc().getChecksum() & ((1 << kHashBits) - 1); 178 const GrProgramDesc& a = fEntries[i]->fProgram->getDesc(); 179 const GrProgramDesc& b = fEntries[i + 1]->fProgram->getDesc();
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H A D | GrGLProgram.h | 49 const GrProgramDesc& getDesc() { return fDesc; } function in class:GrGLProgram
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64DeadRegisterDefinitionsPass.cpp | 79 for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) { 99 switch (MI.getDesc().OpInfo[i].RegClass) {
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/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/stringprep/ |
H A D | TestInputDataStructure.java | 36 public String getDesc() { method in class:TestInputDataStructure
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/external/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); 105 unsigned SchedClass = MI->getDesc().getSchedClass(); 168 unsigned DefClass = DefMI->getDesc().getSchedClass(); 212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
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H A D | DFAPacketizer.cpp | 92 const llvm::MCInstrDesc &MID = MI->getDesc(); 99 const llvm::MCInstrDesc &MID = MI->getDesc();
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H A D | TargetInstrInfo.cpp | 124 const MCInstrDesc &MCID = MI->getDesc(); 148 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { 153 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { 187 const MCInstrDesc &MCID = MI->getDesc(); 222 const MCInstrDesc &MCID = MI->getDesc(); 758 unsigned Class = MI->getDesc().getSchedClass(); 793 return ItinData->getStageLatency(MI->getDesc().getSchedClass()); 802 unsigned DefClass = DefMI->getDesc().getSchedClass(); 813 unsigned DefClass = DefMI->getDesc().getSchedClass(); 814 unsigned UseClass = UseMI->getDesc() [all...] |
H A D | ExecutionDepsFix.cpp | 512 const MCInstrDesc &MCID = MI->getDesc(); 585 for (unsigned i = mi->getDesc().getNumDefs(), 586 e = mi->getDesc().getNumOperands(); i != e; ++i) { 595 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { 614 for (unsigned i = mi->getDesc().getNumDefs(), 615 e = mi->getDesc().getNumOperands(); i != e; ++i) {
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H A D | PeepholeOptimizer.cpp | 272 assert(DefIdx < Def->getDesc().getNumDefs() && 883 assert(MI->getDesc().getNumDefs() == 1 && 996 const MCInstrDesc &MCID = MI->getDesc(); 1016 const MCInstrDesc &MCID = MI->getDesc(); 1037 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 1150 const MCInstrDesc &MIDesc = MI->getDesc(); 1220 if (Def->getDesc().getNumDefs() != 1) 1412 (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) &&
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonVLIWPacketizer.cpp | 380 return (MI->getDesc().isTerminator() || MI->getDesc().isCall()); 411 const MCInstrDesc& TID = MI->getDesc(); 493 if (MI->getDesc().mayLoad()) { 499 if (MI->getDesc().mayStore()) { 550 const MCInstrDesc& MCID = PacketMI->getDesc(); 561 if (PacketSU->getInstr()->getDesc().mayStore() || 578 MI->getDesc().mayStore() && 584 PacketMI->getDesc().mayLoad() && 959 const MCInstrDesc& TID = MI->getDesc(); [all...] |
H A D | HexagonInstrInfo.cpp | 679 const MCInstrDesc &MID = MI->getDesc(); 701 const uint64_t F = MI->getDesc().TSFlags; 715 return MI->getDesc().isBranch(); 733 bool isPred = MI->getDesc().isPredicable(); 837 const uint64_t F = MI->getDesc().TSFlags; 1054 const uint64_t F = MI->getDesc().TSFlags; 1066 const uint64_t F = MI->getDesc().TSFlags; 1083 const uint64_t F = MI->getDesc().TSFlags; 1098 const uint64_t F = MI->getDesc().TSFlags; 1282 // return MI->getDesc() [all...] |
/external/llvm/include/llvm/Support/ |
H A D | Registry.h | 35 const char *getDesc() const { return Desc; } function in class:llvm::SimpleRegistryEntry 52 static const char *descof(const entry &Entry) { return Entry.getDesc(); }
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/external/llvm/include/llvm/ADT/ |
H A D | Statistic.h | 44 const char *getDesc() const { return Desc; } function in class:llvm::Statistic
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/external/skia/src/gpu/ |
H A D | GrPathRendering.cpp | 71 SkDescriptor* genericDesc = ad.getDesc();
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 72 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift; 114 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift; 125 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineInstr.h | 270 /// getDesc - Returns the target instruction descriptor of this 272 const MCInstrDesc &getDesc() const { return *MCID; } function in class:llvm::MachineInstr 329 operands_begin(), operands_begin() + getDesc().getNumDefs()); 333 operands_begin(), operands_begin() + getDesc().getNumDefs()); 337 operands_begin() + getDesc().getNumDefs(), operands_end()); 341 operands_begin() + getDesc().getNumDefs(), operands_end()); 379 return getDesc().getFlags() & (1 << MCFlag);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 265 return MI->getDesc().getSize(); 284 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J)
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