Searched refs:hw (Results 1 - 25 of 108) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_cmdbuf.c61 make_empty_list(&rmesa->radeon.hw.atomlist);
62 rmesa->radeon.hw.atomlist.name = "atom-list";
64 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx );
65 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.set );
66 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin );
67 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw
[all...]
H A Dr200_state_init.c338 if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE)
625 rmesa->radeon.hw.max_state_size = 0;
629 rmesa->hw.ATOM.cmd_size = SZ; \
630 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
631 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
632 rmesa->hw.ATOM.name = NM; \
633 rmesa->hw.ATOM.idx = IDX; \
635 rmesa->hw.ATOM.check = check_##CHK; \
636 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
638 rmesa->hw
[all...]
H A Dr200_state.c70 int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC];
107 rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc;
119 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3] );
205 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &
218 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE;
219 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func;
220 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func;
223 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE;
226 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl;
227 rmesa->hw
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H A Dr200_ioctl.h88 rmesa->hw.ATOM.dirty = GL_TRUE; \
89 rmesa->radeon.hw.is_dirty = GL_TRUE; \
96 if (__dword != (rmesa)->hw.ATOM.cmd[__index]) { \
98 (rmesa)->hw.ATOM.cmd[__index] = __dword; \
103 memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \
104 rmesa->hw.ATOM.cmd_size * 4)
114 rmesa->radeon.hw.is_dirty = GL_TRUE;
H A Dradeon_queryobj.h52 radeon->hw.max_state_size += (SZ);
53 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
H A Dr200_fragshader.c135 afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd;
138 afs_cmd = (GLuint *) rmesa->hw.afs[0].cmd;
320 afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd;
341 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_MULTI_PASS_ENABLE |
344 rmesa->hw.cst.cmd[CST_PP_CNTL_X] &= ~(R200_PPX_PFS_INST_ENABLE_MASK |
351 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[0] == 8 ?
355 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_MULTI_PASS_ENABLE;
356 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[1] == 8 ?
359 rmesa->hw.cst.cmd[CST_PP_CNTL_X] |=
367 rmesa->hw
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/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_ioctl.c69 make_empty_list(&rmesa->radeon.hw.atomlist);
70 rmesa->radeon.hw.atomlist.name = "atom-list";
72 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx);
73 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set);
74 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lin);
75 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw
[all...]
H A Dradeon_state_init.c512 rmesa->radeon.hw.max_state_size = 0;
516 rmesa->hw.ATOM.cmd_size = SZ; \
517 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
518 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
519 rmesa->hw.ATOM.name = NM; \
520 rmesa->hw.ATOM.is_tcl = FLAG; \
521 rmesa->hw.ATOM.check = check_##CHK; \
522 rmesa->hw.ATOM.dirty = GL_TRUE; \
523 rmesa->hw.ATOM.idx = IDX; \
524 rmesa->radeon.hw
[all...]
H A Dradeon_state.c69 int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC];
106 rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc;
113 GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~RADEON_COMB_FCN_MASK;
139 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b;
142 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE;
144 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
154 GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] &
252 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b;
266 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_TEST_MASK;
270 rmesa->hw
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H A Dradeon_ioctl.h105 rmesa->hw.ATOM.dirty = GL_TRUE; \
106 rmesa->radeon.hw.is_dirty = GL_TRUE; \
110 memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \
111 rmesa->hw.ATOM.cmd_size * 4)
120 rmesa->radeon.hw.is_dirty = GL_TRUE;
H A Dradeon_queryobj.h52 radeon->hw.max_state_size += (SZ);
53 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
/external/mesa3d/src/mesa/drivers/dri/nouveau/
H A Dnv04_context.c52 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; local
64 fahrenheit = hw->eng3dm;
66 fahrenheit = hw->eng3d;
80 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; local
82 struct nv04_fifo *fifo = hw->chan->data;
85 PUSH_DATA (push, hw->surf3d->handle);
87 PUSH_DATA (push, hw->ntfy->handle);
92 PUSH_DATA (push, hw
145 struct nouveau_hw_state *hw; local
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H A Dnv04_surface.c204 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; local
205 struct nouveau_object *swzsurf = hw->swzsurf;
206 struct nv04_fifo *fifo = hw->chan->data;
269 PUSH_DATA (push, hw->surf3d->handle);
285 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; local
286 struct nv04_fifo *fifo = hw->chan->data;
433 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; local
466 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; local
482 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; local
[all...]
H A Dnouveau_context.h77 struct nouveau_hw_state hw; member in struct:nouveau_context
94 (to_nouveau_context(ctx)->hw.chan)
96 (to_nouveau_context(ctx)->hw.client)
98 (to_nouveau_context(ctx)->hw.pushbuf)
100 (to_nouveau_context(ctx)->hw.eng3d)
H A Dnouveau_context.c154 }, sizeof(struct nv04_fifo), &nctx->hw.chan);
161 ret = nouveau_client_new(context_dev(ctx), &nctx->hw.client);
168 ret = nouveau_pushbuf_new(nctx->hw.client, nctx->hw.chan, 4,
169 512 * 1024, true, &nctx->hw.pushbuf);
176 ret = nouveau_bufctx_new(nctx->hw.client, 16, &nctx->hw.bufctx);
182 nctx->hw.pushbuf->user_priv = nctx->hw.bufctx;
185 ret = nouveau_object_new(nctx->hw
[all...]
H A Dnv04_state_frag.c57 uint32_t hw; member in struct:combiner_state
76 (rc)->hw = 0; \
166 (rc)->hw |= ((flags & INVERT ? COMBINER_INVERT : 0) | \
172 (rc)->hw |= get_input_arg(rc, arg, flags) << COMBINER_SHIFT(in)
175 (rc)->hw |= ((rc)->logscale ? \
179 (rc)->hw |= ((rc)->logscale ? \
295 nv04->alpha[i] = rc_a.hw;
296 nv04->color[i] = rc_c.hw;
/external/mesa3d/src/gallium/drivers/nv30/
H A Dnvfx_fragprog.c90 uint32_t *hw = &fp->insn[fpc->inst_offset]; local
96 hw[0] |= (src.reg.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
108 hw = &fp->insn[fpc->inst_offset];
121 hw = &fp->insn[fpc->inst_offset];
149 hw[1] |= (1 << (29 + pos));
156 hw[pos + 1] |= sr;
163 uint32_t *hw = &fp->insn[fpc->inst_offset]; local
170 hw[0] |= NVFX_FP_OP_OUT_REG_HALF;
179 hw[0] |= (1 << 30);
185 hw[
192 uint32_t *hw; local
242 uint32_t *hw; local
269 uint32_t *hw; local
288 uint32_t *hw; local
305 uint32_t *hw; local
332 uint32_t *hw; local
356 uint32_t *hw; local
817 uint32_t *hw; local
828 uint32_t *hw; local
915 unsigned hw; local
954 unsigned hw; local
988 unsigned hw; local
[all...]
H A Dnv30_format.h9 unsigned hw; member in struct:nv30_format
13 unsigned hw; member in struct:nv30_vtxfmt
H A Dnvfx_vertprog.c117 emit_src(struct nv30_context *nv30, struct nvfx_vpc *vpc, uint32_t *hw, argument
133 hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
143 hw[1] |= (src.reg.index << NVFX_VP(INST_CONST_SRC_SHIFT)) &
159 hw[0] |= (1 << (21 + pos));
168 hw[3] |= NVFX_VP(INST_INDEX_CONST);
170 hw[0] |= NVFX_VP(INST_INDEX_INPUT);
175 hw[0] |= NVFX_VP(INST_ADDR_REG_SELECT_1);
176 hw[0] |= src.indirect_swz << NVFX_VP(INST_ADDR_SWZ_SHIFT);
181 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
183 hw[
201 emit_dst(struct nv30_context *nv30, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_reg dst) argument
297 uint32_t *hw; local
822 int hw = 0, i; local
[all...]
H A Dnv30_query.c36 struct nouveau_heap *hw; member in struct:nv30_query_object
46 if (qo && qo->hw)
47 ntfy = (char *)notify->map + query->offset + qo->hw->start;
60 nouveau_heap_free(&qo->hw);
75 /* allocate a new hw query object, if no hw objects left we need to
78 while (nouveau_heap_alloc(screen->query_heap, 32, NULL, &qo->hw)) {
159 PUSH_DATA (push, (q->report << 24) | q->qo[0]->hw->start);
187 PUSH_DATA (push, (q->report << 24) | q->qo[1]->hw->start);
254 PUSH_DATA (push, 0x02000000 | q->qo[1]->hw
[all...]
/external/dhcpcd/
H A Dduid.c46 uint16_t hw = 0; local
79 hw = htons(iface->family);
80 memcpy(p, &hw, 2);
/external/wpa_supplicant_8/hostapd/src/ap/
H A Dhw_features.c508 u16 hw = iface->current_mode->ht_capab; local
512 !(hw & HT_CAP_INFO_LDPC_CODING_CAP)) {
523 !(hw & HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET)) {
550 !(hw & HT_CAP_INFO_GREEN_FIELD)) {
557 !(hw & HT_CAP_INFO_SHORT_GI20MHZ)) {
564 !(hw & HT_CAP_INFO_SHORT_GI40MHZ)) {
570 if ((conf & HT_CAP_INFO_TX_STBC) && !(hw & HT_CAP_INFO_TX_STBC)) {
577 (hw & HT_CAP_INFO_RX_STBC_MASK)) {
584 !(hw & HT_CAP_INFO_DELAYED_BA)) {
591 !(hw
617 ieee80211ac_cap_check(u32 hw, u32 conf, u32 cap, const char *name) argument
635 ieee80211ac_cap_check_max(u32 hw, u32 conf, u32 mask, unsigned int shift, const char *name) argument
654 u32 hw = mode->vht_capab; local
[all...]
/external/wpa_supplicant_8/src/ap/
H A Dhw_features.c508 u16 hw = iface->current_mode->ht_capab; local
512 !(hw & HT_CAP_INFO_LDPC_CODING_CAP)) {
523 !(hw & HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET)) {
550 !(hw & HT_CAP_INFO_GREEN_FIELD)) {
557 !(hw & HT_CAP_INFO_SHORT_GI20MHZ)) {
564 !(hw & HT_CAP_INFO_SHORT_GI40MHZ)) {
570 if ((conf & HT_CAP_INFO_TX_STBC) && !(hw & HT_CAP_INFO_TX_STBC)) {
577 (hw & HT_CAP_INFO_RX_STBC_MASK)) {
584 !(hw & HT_CAP_INFO_DELAYED_BA)) {
591 !(hw
617 ieee80211ac_cap_check(u32 hw, u32 conf, u32 cap, const char *name) argument
635 ieee80211ac_cap_check_max(u32 hw, u32 conf, u32 mask, unsigned int shift, const char *name) argument
654 u32 hw = mode->vht_capab; local
[all...]
/external/wpa_supplicant_8/wpa_supplicant/src/ap/
H A Dhw_features.c508 u16 hw = iface->current_mode->ht_capab; local
512 !(hw & HT_CAP_INFO_LDPC_CODING_CAP)) {
523 !(hw & HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET)) {
550 !(hw & HT_CAP_INFO_GREEN_FIELD)) {
557 !(hw & HT_CAP_INFO_SHORT_GI20MHZ)) {
564 !(hw & HT_CAP_INFO_SHORT_GI40MHZ)) {
570 if ((conf & HT_CAP_INFO_TX_STBC) && !(hw & HT_CAP_INFO_TX_STBC)) {
577 (hw & HT_CAP_INFO_RX_STBC_MASK)) {
584 !(hw & HT_CAP_INFO_DELAYED_BA)) {
591 !(hw
617 ieee80211ac_cap_check(u32 hw, u32 conf, u32 cap, const char *name) argument
635 ieee80211ac_cap_check_max(u32 hw, u32 conf, u32 mask, unsigned int shift, const char *name) argument
654 u32 hw = mode->vht_capab; local
[all...]
/external/mesa3d/src/gallium/drivers/svga/
H A Dsvga_state_framebuffer.c46 struct pipe_framebuffer_state *hw = &svga->state.hw_clear.framebuffer; local
57 if (curr->cbufs[i] != hw->cbufs[i] ||
58 (reemit && hw->cbufs[i])) {
66 pipe_surface_reference(&hw->cbufs[i], curr->cbufs[i]);
71 if (curr->zsbuf != hw->zsbuf ||
72 (reemit && hw->zsbuf)) {
89 pipe_surface_reference(&hw->zsbuf, curr->zsbuf);
109 struct pipe_framebuffer_state *hw = &svga->state.hw_clear.framebuffer; local
116 if (hw->cbufs[i]) {
117 ret = SVGA3D_SetRenderTarget(svga->swc, SVGA3D_RT_COLOR0 + i, hw
[all...]

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