| /external/llvm/lib/CodeGen/ |
| H A D | DeadMachineInstructionElim.cpp | 46 bool isDead(const MachineInstr *MI) const;
55 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { function in class:DeadMachineInstructionElim
127 if (isDead(MI)) {
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| H A D | MachineInstrBundle.cpp | 163 if (MO.isDead()) {
169 if (!MO.isDead())
174 if (!MO.isDead()) {
191 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg); local
192 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
320 if (!MO.isDead())
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| H A D | LivePhysRegs.cpp | 75 if (!O->isDead())
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| H A D | MachineCSE.cpp | 257 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
545 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
550 if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
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| H A D | PHIElimination.cpp | 236 bool isDead = MPhi->getOperand(0).isDead(); local
304 if (isDead) {
332 if (DestLI.endIndex().isDead()) {
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| H A D | MachineInstr.cpp | 148 bool isKill, bool isDead, bool isUndef,
168 IsDead = isDead;
285 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
311 if (isDead()) {
872 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
1171 /// the specified register or -1 if it is not found. If isDead is true, defs
1175 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, argument
1195 if (Found && (!isDead || MO.isDead()))
147 ChangeToRegister(unsigned Reg, bool isDef, bool isImp, bool isKill, bool isDead, bool isUndef, bool isDebug) argument
[all...] |
| H A D | TailDuplication.cpp | 103 void UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead,
232 bool isDead = MBB->pred_empty() && !MBB->hasAddressTaken(); local
234 UpdateSuccessorsPHIs(MBB, isDead, TDBBs, Succs);
237 if (isDead) {
463 TailDuplicatePass::UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead, argument
486 if (isDead) {
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| H A D | RegAllocFast.cpp | 649 } else if (MO.isDead()) {
660 } else if (MO.isDead()) {
676 bool Dead = MO.isDead();
947 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
1033 definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
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| H A D | LiveInterval.cpp | 63 assert(!Def.isDead() && "Cannot define a value at the dead slot");
535 bool isDead = true;
538 isDead = false;
541 if (isDead) {
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| H A D | LiveIntervalAnalysis.cpp | 1138 if (I->end.isDead()) {
1150 if (!I->end.isDead()) {
1291 if (LII->end.isDead()) {
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| H A D | MachineLICM.cpp | 469 if (!MO.isDead())
982 } else if (!MO.isDead()) {
1428 if (MO.isReg() && MO.isDef() && !MO.isDead())
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| H A D | MachineVerifier.cpp | 1098 if (MO->isDead())
1127 if (MO->isDead()) {
1533 if (S.end.isDead()) {
1572 if (!S.end.isDead()) {
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| H A D | RegisterScavenging.cpp | 142 if (!isPred && MO.isDead())
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| H A D | VirtRegMap.cpp | 384 if (MO.isDead())
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 289 bool isDead() const { function in class:llvm::MachineOperand
537 /// operand. Note: This method ignores isKill and isDead properties.
561 bool isKill = false, bool isDead = false,
587 bool isKill = false, bool isDead = false,
593 assert(!(isDead && !isDef) && "Dead flag on non-def");
599 Op.IsDead = isDead;
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| H A D | MachineInstr.h | 902 /// the specified register or -1 if it is not found. If isDead is true, defs
908 bool isDead = false, bool Overlap = false,
913 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
915 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64DeadRegisterDefinitionsPass.cpp | 81 if (MO.isReg() && MO.isDead() && MO.isDef()) {
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| H A D | AArch64ExpandPseudoInsts.cpp | 107 const bool DstIsDead = MI.getOperand(0).isDead();
172 const bool DstIsDead = MI.getOperand(0).isDead();
355 const bool DstIsDead = MI.getOperand(0).isDead();
524 bool DstIsDead = MI.getOperand(0).isDead();
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| H A D | AArch64ConditionOptimizer.cpp | 158 if (I->getOperand(0).isDead())
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 396 bool isDead = false) {
397 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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| H A D | Thumb2SizeReduction.cpp | 702 if (HasCC && MI->getOperand(NumOps-1).isDead())
798 if (HasCC && MI->getOperand(NumOps-1).isDead())
866 if (!MO.isDead())
976 if (MO && !MO->isDead())
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| H A D | ARMExpandPseudoInsts.cpp | 393 bool DstIsDead = MI.getOperand(OpIdx).isDead();
527 DstIsDead = MI.getOperand(OpIdx).isDead();
659 bool DstIsDead = MI.getOperand(0).isDead();
954 bool DstIsDead = MI.getOperand(0).isDead();
976 bool DstIsDead = MI.getOperand(0).isDead();
1029 bool DstIsDead = MI.getOperand(0).isDead();
1091 bool DstIsDead = MI.getOperand(OpIdx).isDead();
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| /external/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | SimpleStreamChecker.cpp | 192 bool IsSymDead = SymReaper.isDead(Sym);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 233 false /*isDead*/,
322 Src.isKill(), Src.isDead(), Src.isUndef(),
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| H A D | HexagonHardwareLoops.cpp | 164 bool isDead(const MachineInstr *MI,
884 /// copied from DeadMachineInstructionElim::isDead, but with special cases
887 bool HexagonHardwareLoops::isDead(const MachineInstr *MI, function in class:HexagonHardwareLoops
939 if (isDead(MI, DeadPhis)) {
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