Searched refs:s32 (Results 1 - 25 of 144) sorted by relevance

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/external/lldb/test/lang/cpp/char1632_t/
H A Dmain.cpp16 char32_t *s32 = (char32_t *)U"ЕЙРГЖО"; local
17 s32 = nullptr; // Set break point at this line.
18 s32 = (char32_t *)U"෴";
/external/lldb/test/lang/cpp/rdar12991846/
H A Dmain.cpp16 char32_t *s32 = (char32_t *)U"ЕЙРГЖО"; local
17 s32 = nullptr; // Set break point at this line.
18 s32 = (char32_t *)U"෴";
/external/neven/FaceRecEm/common/src/b_FDSDK/
H A DTypes.h38 typedef signed int s32; typedef
43 typedef signed long s32; typedef
48 typedef signed int s32; typedef
54 typedef s32 s16p16;
57 typedef s32 s8p24;
/external/libhevc/common/arm/
H A Dihevc_itrans_recon_8x8.s242 vadd.s32 q5,q10,q11 @// c0 = y0 * cos4 + y4 * cos4(part of a0 and a1)
243 vsub.s32 q10,q10,q11 @// c1 = y0 * cos4 - y4 * cos4(part of a0 and a1)
250 vadd.s32 q7,q5,q3 @// a0 = c0 + d0(part of r0,r7)
251 vsub.s32 q5,q5,q3 @// a3 = c0 - d0(part of r3,r4)
252 vsub.s32 q11,q10,q9 @// a2 = c1 - d1(part of r2,r5)
253 vadd.s32 q9,q10,q9 @// a1 = c1 + d1(part of r1,r6)
255 vadd.s32 q10,q7,q12 @// a0 + b0(part of r0)
256 vsub.s32 q3,q7,q12 @// a0 - b0(part of r7)
258 vadd.s32 q12,q11,q14 @// a2 + b2(part of r2)
259 vsub.s32 q1
[all...]
H A Dihevc_itrans_recon_4x4.s160 vshl.s32 q5,q5,#6 @e[0] = 64*(pi2_src[0] + pi2_src[2])
161 vshl.s32 q6,q6,#6 @e[1] = 64*(pi2_src[0] - pi2_src[2])
163 vadd.s32 q7,q5,q3 @((e[0] + o[0] )
164 vadd.s32 q8,q6,q4 @((e[1] + o[1])
165 vsub.s32 q9,q6,q4 @((e[1] - o[1])
166 vsub.s32 q10,q5,q3 @((e[0] - o[0])
168 vqrshrn.s32 d0,q7,#shift_stage1_idct @pi2_out[0] = clip_s16((e[0] + o[0] + add)>>shift) )
169 vqrshrn.s32 d1,q8,#shift_stage1_idct @pi2_out[1] = clip_s16((e[1] + o[1] + add)>>shift) )
170 vqrshrn.s32 d2,q9,#shift_stage1_idct @pi2_out[2] = clip_s16((e[0] - o[0] + add)>>shift) )
171 vqrshrn.s32 d
[all...]
H A Dihevc_weighted_pred_bi.s170 vneg.s32 q14,q14
195 vadd.s32 q2,q2,q4 @vaddq_s32(i4_tmp1_t1, i4_tmp1_t2)
201 vadd.s32 q2,q2,q15 @vaddq_s32(i4_tmp1_t1, tmp_lvl_shift_t)
206 vshl.s32 q2,q2,q14 @vshlq_s32(i4_tmp1_t1, tmp_shift_t)
209 vadd.s32 q5,q5,q6 @vaddq_s32(i4_tmp2_t1, i4_tmp2_t2) ii iteration
211 vqmovun.s32 d4,q2 @vqmovun_s32(sto_res_tmp1)
214 vadd.s32 q5,q5,q15 @vaddq_s32(i4_tmp2_t1, tmp_lvl_shift_t) ii iteration
215 vmov.s32 d5,d4 @vcombine_u16(sto_res_tmp2, sto_res_tmp2)
216 vadd.s32 q7,q7,q8 @vaddq_s32(i4_tmp1_t1, i4_tmp1_t2) iii iteration
218 vshl.s32 q
[all...]
/external/llvm/test/MC/ARM/
H A Dneon-convert-encoding.s3 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
4 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
8 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
12 vcvt.s32.f32 q8, q8
15 @ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3]
16 vcvt.f32.s32 q8, q8
19 @ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2]
20 vcvt.s32
[all...]
H A Dbasic-arm-instructions-v8.1a.s50 vqrdmlah.s32 d0, d1, d2
51 //CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x12,0x0b,0x21,0xf3]
52 //CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0b]
54 //CHECK-V8: vqrdmlah.s32 d0, d1, d2
64 vqrdmlah.s32 q2, q3, q0
65 //CHECK-V81aARM: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x50,0x4b,0x26,0xf3]
66 //CHECK-V81aTHUMB: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x26,0xff,0x50,0x4b]
68 //CHECK-V8: vqrdmlah.s32 q2, q3, q0
79 vqrdmlsh.s32 d0, d1, d2
80 //CHECK-V81aARM: vqrdmlsh.s32 d
[all...]
H A Dneont2-cmp-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
17 @ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x06]
18 vcvt.f32.s32 q8, q8
21 @ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0f]
22 vcvt.s32
[all...]
H A Dneont2-convert-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
17 @ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x06]
18 vcvt.f32.s32 q8, q8
21 @ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0f]
22 vcvt.s32
[all...]
H A Dneon-abs-encoding.s7 @ CHECK: vabs.s32 d16, d16 @ encoding: [0x20,0x03,0xf9,0xf3]
8 vabs.s32 d16, d16
15 @ CHECK: vabs.s32 q8, q8 @ encoding: [0x60,0x03,0xf9,0xf3]
16 vabs.s32 q8, q8
24 @ CHECK: vqabs.s32 d16, d16 @ encoding: [0x20,0x07,0xf8,0xf3]
25 vqabs.s32 d16, d16
30 @ CHECK: vqabs.s32 q8, q8 @ encoding: [0x60,0x07,0xf8,0xf3]
31 vqabs.s32 q8, q8
H A Dneon-neg-encoding.s7 @ CHECK: vneg.s32 d16, d16 @ encoding: [0xa0,0x03,0xf9,0xf3]
8 vneg.s32 d16, d16
15 @ CHECK: vneg.s32 q8, q8 @ encoding: [0xe0,0x03,0xf9,0xf3]
16 vneg.s32 q8, q8
23 @ CHECK: vqneg.s32 d16, d16 @ encoding: [0xa0,0x07,0xf8,0xf3]
24 vqneg.s32 d16, d16
29 @ CHECK: vqneg.s32 q8, q8 @ encoding: [0xe0,0x07,0xf8,0xf3]
30 vqneg.s32 q8, q8
H A Dneont2-abs-encoding.s9 @ CHECK: vabs.s32 d16, d16 @ encoding: [0xf9,0xff,0x20,0x03]
10 vabs.s32 d16, d16
17 @ CHECK: vabs.s32 q8, q8 @ encoding: [0xf9,0xff,0x60,0x03]
18 vabs.s32 q8, q8
26 @ CHECK: vqabs.s32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x07]
27 vqabs.s32 d16, d16
32 @ CHECK: vqabs.s32 q8, q8 @ encoding: [0xf8,0xff,0x60,0x07]
33 vqabs.s32 q8, q8
H A Dneont2-neg-encoding.s9 @ CHECK: vneg.s32 d16, d16 @ encoding: [0xf9,0xff,0xa0,0x03]
10 vneg.s32 d16, d16
17 @ CHECK: vneg.s32 q8, q8 @ encoding: [0xf9,0xff,0xe0,0x03]
18 vneg.s32 q8, q8
25 @ CHECK: vqneg.s32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x07]
26 vqneg.s32 d16, d16
31 @ CHECK: vqneg.s32 q8, q8 @ encoding: [0xf8,0xff,0xe0,0x07]
32 vqneg.s32 q8, q8
H A Dneon-v8.s12 vcvta.s32.f32 d4, d6
13 @ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0x06,0x40,0xbb,0xf3]
16 vcvta.s32.f32 q4, q6
17 @ CHECK: vcvta.s32.f32 q4, q6 @ encoding: [0x4c,0x80,0xbb,0xf3]
21 vcvtm.s32.f32 d1, d30
22 @ CHECK: vcvtm.s32.f32 d1, d30 @ encoding: [0x2e,0x13,0xbb,0xf3]
25 vcvtm.s32.f32 q1, q10
26 @ CHECK: vcvtm.s32.f32 q1, q10 @ encoding: [0x64,0x23,0xbb,0xf3]
30 vcvtn.s32.f32 d15, d17
31 @ CHECK: vcvtn.s32
[all...]
/external/linux-tools-perf/src/tools/perf/util/
H A Dtypes.h13 typedef signed int s32; typedef
/external/compiler-rt/lib/builtins/arm/
H A Dfixsfsivfp.S23 vcvt.s32.f32 s15, s15 // convert single to 32-bit int into s15
H A Dfloatsisfvfp.S23 vcvt.f32.s32 s15, s15 // convert 32-bit int in s15 to float in s15
H A Dfixdfsivfp.S23 vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15
H A Dfloatsidfvfp.S23 vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7
/external/libmpeg2/common/arm/
H A Dimpeg2_idct.s218 vdup.s32 q0, r4
230 vraddhn.s32 d12, q0, q4
231 vraddhn.s32 d13, q0, q5
240 vraddhn.s32 d12, q0, q4
241 vraddhn.s32 d13, q0, q5
250 vraddhn.s32 d12, q0, q4
251 vraddhn.s32 d13, q0, q5
260 vraddhn.s32 d12, q0, q4
261 vraddhn.s32 d13, q0, q5
270 vraddhn.s32 d1
[all...]
/external/libavc/common/arm/
H A Dih264_ihadamard_scaling_a9.s104 vdup.s32 q10, r4 @ Populate the u4_qp_div_6 in Q10
108 vdup.s32 q9, r6 @ Populate pu2_iscal_mat[0]*pu2_weigh_mat[0] 32-bit in Q9
118 vadd.s32 q2, q12, q13 @pi4_tmp_ptr[0] = x0 + x1
119 vadd.s32 q3, q15, q14 @pi4_tmp_ptr[1] = x3 + x2
120 vsub.s32 q4, q12, q13 @pi4_tmp_ptr[2] = x0 - x1
121 vsub.s32 q5, q15, q14 @pi4_tmp_ptr[3] = x3 - x2
130 vadd.s32 q12, q2, q5 @x0 = x4+x7
131 vadd.s32 q13, q3, q4 @x1 = x5+x6
132 vsub.s32 q14, q3, q4 @x2 = x5-x6
133 vsub.s32 q1
[all...]
H A Dih264_resi_trans_quant_a9.s172 vdup.s32 q4, r8 @Load rounding value row 1
178 vdup.s32 q10, r7 @Load qbit values
189 vmov.s32 q5, q4 @copy round fact for row 2
191 vmov.s32 q6, q4 @copy round fact for row 2
194 vmov.s32 q7, q4 @copy round fact for row 2
202 vshl.s32 q11, q4, q10 @Shift row 1
203 vshl.s32 q12, q5, q10 @Shift row 2
204 vshl.s32 q13, q6, q10 @Shift row 3
205 vshl.s32 q14, q7, q10 @Shift row 4
207 vmovn.s32 d3
[all...]
/external/v8/src/base/
H A Ddivision-by-constant-unittest.cc30 static M32 s32(int32_t d) { function in namespace:v8::base
45 EXPECT_EQ(M32(0x99999999U, 1, false), s32(-5));
46 EXPECT_EQ(M32(0x55555555U, 1, false), s32(-3));
50 EXPECT_EQ(M32(0x7FFFFFFFU, k - 1, false), s32(d));
53 EXPECT_EQ(M32(0x80000001U, k - 1, false), s32(1 << k));
55 EXPECT_EQ(M32(0x55555556U, 0, false), s32(3));
56 EXPECT_EQ(M32(0x66666667U, 1, false), s32(5));
57 EXPECT_EQ(M32(0x2AAAAAABU, 0, false), s32(6));
58 EXPECT_EQ(M32(0x92492493U, 2, false), s32(7));
59 EXPECT_EQ(M32(0x38E38E39U, 1, false), s32(
[all...]
/external/libvpx/libvpx/vp9/common/arm/neon/
H A Dvp9_iht8x8_add_neon.asm147 vqrshrn.s32 d8, q2, #14 ; >> 14
148 vqrshrn.s32 d9, q3, #14 ; >> 14
151 vqrshrn.s32 d10, q5, #14 ; >> 14
152 vqrshrn.s32 d11, q6, #14 ; >> 14
171 vqrshrn.s32 d14, q2, #14 ; >> 14
172 vqrshrn.s32 d15, q3, #14 ; >> 14
178 vqrshrn.s32 d12, q9, #14 ; >> 14
179 vqrshrn.s32 d13, q13, #14 ; >> 14
201 vqrshrn.s32 d18, q2, #14 ; >> 14
202 vqrshrn.s32 d1
[all...]

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