Searched refs:shift_type (Results 1 - 8 of 8) sorted by relevance
/external/lldb/source/Plugins/Instruction/ARM/ |
H A D | EmulateInstructionARM.h | 548 EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type); 552 EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type);
|
H A D | EmulateInstructionARM.cpp | 3177 EmulateInstructionARM::EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type) argument 3179 // assert(shift_type == SRType_ASR 3180 // || shift_type == SRType_LSL 3181 // || shift_type == SRType_LSR 3182 // || shift_type == SRType_ROR 3183 // || shift_type == SRType_RRX); 3198 if (shift_type == SRType_ROR && use_encoding == eEncodingT1) 3208 if (shift_type == SRType_ROR) 3219 if (shift_type == SRType_RRX) 3240 if (shift_type 3267 EmulateShiftReg(const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type) argument [all...] |
/external/v8/src/arm64/ |
H A D | simulator-arm64.cc | 891 T Simulator::ShiftOperand(T value, Shift shift_type, unsigned amount) { argument 898 switch (shift_type) { 1394 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); local 1398 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); 1401 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); 1440 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); local 1444 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); 1448 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount);
|
H A D | simulator-arm64.h | 696 Shift shift_type,
|
/external/vixl/src/vixl/a64/ |
H A D | simulator-a64.h | 1418 Shift shift_type, 1422 Shift shift_type,
|
H A D | simulator-a64.cc | 334 Shift shift_type, 340 switch (shift_type) { 983 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); local 985 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type,
|
/external/valgrind/VEX/priv/ |
H A D | guest_arm_toIR.c | 9066 UInt regD = 99, regN = 99, regM = 99, imm5 = 99, shift_type = 99; local 9077 shift_type = (INSNT1(5,5) << 1) | 0; 9090 shift_type = (INSNA(6,6) << 1) | 0; 9102 dis_buf, &irt_regM_shift, NULL, irt_regM, shift_type, imm5, regM ); 9126 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; local 9135 shift_type = (INSNT0(5,5) << 1) | 0; 9140 if (shift_type == BITS2(1,0) && imm5 == 0) 9148 shift_type = (INSNA(6,6) << 1) | 0; 9165 irt_regN, shift_type, imm5, regN ); 9184 UInt regD = 99, regN = 99, shift_type local [all...] |
/external/v8/src/arm/ |
H A D | simulator-arm.cc | 2607 int32_t shift_type = instr->Bit(6); local 2609 if (shift_type == 0) { // LSL
|
Completed in 856 milliseconds