/external/clang/test/CodeGen/ |
H A D | arm-neon-misc.c | 24 void t2(uint64_t *src1, uint8_t *src2, uint64x2_t *dst) { argument 26 uint64x2_t q = vld1q_u64(src1);
|
/external/skia/tests/ |
H A D | CPlusPlusEleven.cpp | 24 Moveable src1; Moveable dst1(Move(src1)); local
|
/external/pcre/dist/sljit/ |
H A D | sljitNativePPC_32.c | 45 sljit_si dst, sljit_si src1, sljit_si src2) 52 SLJIT_ASSERT(src1 == TMP_REG1); 59 SLJIT_ASSERT(src1 == TMP_REG1); 74 SLJIT_ASSERT(src1 == TMP_REG1); 86 SLJIT_ASSERT(src1 == TMP_REG1); 90 SLJIT_ASSERT(src1 == TMP_REG1); 94 SLJIT_ASSERT(src1 == TMP_REG1); 101 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); 106 return push_inst(compiler, ADDIS | D(dst) | A(src1) | compiler->imm); 110 return push_inst(compiler, ADDIC | D(dst) | A(src1) | compile 44 emit_single_op(struct sljit_compiler *compiler, sljit_si op, sljit_si flags, sljit_si dst, sljit_si src1, sljit_si src2) argument [all...] |
H A D | sljitNativeMIPS_64.c | 127 FAIL_IF(push_inst(compiler, op_imm | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); \ 129 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \ 133 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)); \ 135 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \ 148 FAIL_IF(push_inst(compiler, ins | T(src1) | DA(EQUAL_FLAG) | SH_IMM(src2), EQUAL_FLAG)); \ 150 FAIL_IF(push_inst(compiler, ins | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \ 155 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); \ 157 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | D(dst), DR(dst))); \ 161 sljit_si dst, sljit_si src1, sljit_sw src2) 168 SLJIT_ASSERT(src1 160 emit_single_op(struct sljit_compiler *compiler, sljit_si op, sljit_si flags, sljit_si dst, sljit_si src1, sljit_sw src2) argument [all...] |
H A D | sljitNativePPC_64.c | 133 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \ 134 src1 = TMP_REG1; \ 144 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \ 145 src1 = TMP_REG1; \ 149 sljit_si dst, sljit_si src1, sljit_si src2) 154 SLJIT_ASSERT(src1 == TMP_REG1); 161 SLJIT_ASSERT(src1 == TMP_REG1); 174 SLJIT_ASSERT(src1 == TMP_REG1); 189 SLJIT_ASSERT(src1 == TMP_REG1); 201 SLJIT_ASSERT(src1 148 emit_single_op(struct sljit_compiler *compiler, sljit_si op, sljit_si flags, sljit_si dst, sljit_si src1, sljit_si src2) argument [all...] |
H A D | sljitNativeSPARC_32.c | 39 sljit_si dst, sljit_si src1, sljit_sw src2) 48 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 55 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 68 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 78 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 82 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); 97 return push_inst(compiler, ADD | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst) | (flags & SET_FLAGS)); 100 return push_inst(compiler, ADDC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst) | (flags & SET_FLAGS)); 103 return push_inst(compiler, SUB | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst) | (flags & SET_FLAGS)); 106 return push_inst(compiler, SUBC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG 38 emit_single_op(struct sljit_compiler *compiler, sljit_si op, sljit_si flags, sljit_si dst, sljit_si src1, sljit_sw src2) argument [all...] |
H A D | sljitNativeMIPS_32.c | 44 FAIL_IF(push_inst(compiler, op_imm | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); \ 46 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \ 50 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)); \ 52 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \ 58 FAIL_IF(push_inst(compiler, op_imm | T(src1) | DA(EQUAL_FLAG) | SH_IMM(src2), EQUAL_FLAG)); \ 60 FAIL_IF(push_inst(compiler, op_imm | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \ 64 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); \ 66 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | D(dst), DR(dst))); \ 70 sljit_si dst, sljit_si src1, sljit_sw src2) 77 SLJIT_ASSERT(src1 69 emit_single_op(struct sljit_compiler *compiler, sljit_si op, sljit_si flags, sljit_si dst, sljit_si src1, sljit_sw src2) argument [all...] |
/external/opencv/cxcore/src/ |
H A D | cxcmp.cpp | 57 worktype a1 = _toggle_macro_(src1[x]), \ 67 worktype a1 = _toggle_macro_(src1[x*2]), \ 70 a1 = _toggle_macro_(src1[x*2+1]); \ 81 worktype a1 = _toggle_macro_(src1[x*3]), \ 84 a1 = _toggle_macro_(src1[x*3+1]); \ 88 a1 = _toggle_macro_(src1[x*3+2]); \ 99 worktype a1 = _toggle_macro_(src1[x*4]), \ 102 a1 = _toggle_macro_(src1[x*4+1]); \ 106 a1 = _toggle_macro_(src1[x*4+2]); \ 110 a1 = _toggle_macro_(src1[ 256 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local 355 CvMat srcstub1, *src1 = (CvMat*)srcarr; local 567 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local 705 CvMat srcstub1, *src1 = (CvMat*)srcarr; local 975 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local 1076 CvMat srcstub1, *src1 = (CvMat*)srcarr; local 1425 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local [all...] |
H A D | cxlogic.cpp | 63 ( const uchar* src1, int step1, const uchar* src2, int step2, \ 64 uchar* dst, int step, CvSize size ), (src1, step1, src2, step2, dst, step, size) )\ 66 for( ; size.height--; src1 += step1, src2 += step2, dst += step ) \ 70 if( (((size_t)src1 | (size_t)src2 | (size_t)dst) & 3) == 0 ) \ 74 int t0 = __op__(((const int*)(src1+i))[0], ((const int*)(src2+i))[0]);\ 75 int t1 = __op__(((const int*)(src1+i))[1], ((const int*)(src2+i))[1]);\ 80 t0 = __op__(((const int*)(src1+i))[2], ((const int*)(src2+i))[2]); \ 81 t1 = __op__(((const int*)(src1+i))[3], ((const int*)(src2+i))[3]); \ 89 int t = __op__(*(const int*)(src1+i), *(const int*)(src2+i)); \ 96 int t = __op__(((const uchar*)src1)[ 352 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local 527 cvXor( const void* src1, const void* src2, void* dst, const void* mask ) argument 544 cvAnd( const void* src1, const void* src2, void* dst, const void* mask ) argument 562 cvOr( const void* src1, const void* src2, void* dst, const void* mask ) argument 573 IPCVAPI_IMPL( CvStatus, icvNot_8u_C1R, ( const uchar* src1, int step1, uchar* dst, int step, CvSize size ), (src1, step1, dst, step, size) ) argument [all...] |
H A D | cxarithm.cpp | 60 worktype t0 = __op__((src1)[i], (src2)[i]); \ 61 worktype t1 = __op__((src1)[i+1], (src2)[i+1]); \ 66 t0 = __op__((src1)[i+2],(src2)[i+2]); \ 67 t1 = __op__((src1)[i+3],(src2)[i+3]); \ 75 worktype t0 = __op__((src1)[i],(src2)[i]); \ 82 ( const type* src1, int step1, const type* src2, int step2, \ 84 (src1, step1, src2, step2, dst, step, size) ) \ 86 step1/=sizeof(src1[0]); step2/=sizeof(src2[0]); step/=sizeof(dst[0]); \ 90 for( ; size.height--; src1 += step1, src2 += step2, dst += step ) \ 92 worktype t0 = __op__((src1)[ 286 CvMat srcstub1, srcstub2, *src1, *src2; local 761 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local 1321 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local 1669 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local 1869 icvAddWeighted_8u_fast_C1R( const uchar* src1, int step1, double alpha, const uchar* src2, int step2, double beta, double gamma, uchar* dst, int step, CvSize size ) argument [all...] |
/external/linux-tools-perf/src/tools/perf/util/include/linux/ |
H A D | bitmap.h | 37 static inline void bitmap_or(unsigned long *dst, const unsigned long *src1, argument 41 *dst = *src1 | *src2; 43 __bitmap_or(dst, src1, src2, nbits);
|
/external/vboot_reference/firmware/stub/ |
H A D | utility_stub.c | 20 int Memcmp(const void *src1, const void *src2, size_t n) argument 22 return memcmp(src1, src2, n);
|
/external/bison/lib/ |
H A D | vbitset.c | 502 vbitset_and (bitset dst, bitset src1, bitset src2) argument 512 vbitset_resize (dst, max (BITSET_SIZE_ (src1), BITSET_SIZE_ (src2))); 515 ssize1 = VBITSET_SIZE (src1); 518 src1p = VBITSET_WORDS (src1); 529 vbitset_and_cmp (bitset dst, bitset src1, bitset src2) argument 540 vbitset_resize (dst, max (BITSET_SIZE_ (src1), BITSET_SIZE_ (src2))); 543 ssize1 = VBITSET_SIZE (src1); 546 src1p = VBITSET_WORDS (src1); 582 vbitset_andn (bitset dst, bitset src1, bitset src2) argument 592 vbitset_resize (dst, max (BITSET_SIZE_ (src1), BITSET_SIZE 622 vbitset_andn_cmp(bitset dst, bitset src1, bitset src2) argument 687 vbitset_or(bitset dst, bitset src1, bitset src2) argument 723 vbitset_or_cmp(bitset dst, bitset src1, bitset src2) argument 778 vbitset_xor(bitset dst, bitset src1, bitset src2) argument 814 vbitset_xor_cmp(bitset dst, bitset src1, bitset src2) argument 872 vbitset_and_or(bitset dst, bitset src1, bitset src2, bitset src3) argument 902 vbitset_and_or_cmp(bitset dst, bitset src1, bitset src2, bitset src3) argument 939 vbitset_andn_or(bitset dst, bitset src1, bitset src2, bitset src3) argument 969 vbitset_andn_or_cmp(bitset dst, bitset src1, bitset src2, bitset src3) argument 1006 vbitset_or_and(bitset dst, bitset src1, bitset src2, bitset src3) argument 1036 vbitset_or_and_cmp(bitset dst, bitset src1, bitset src2, bitset src3) argument [all...] |
H A D | bitset_stats.c | 460 bitset_stats_and (bitset dst, bitset src1, bitset src2) argument 462 BITSET_CHECK3_ (dst, src1, src2); 463 BITSET_AND_ (dst->s.bset, src1->s.bset, src2->s.bset); 468 bitset_stats_and_cmp (bitset dst, bitset src1, bitset src2) argument 470 BITSET_CHECK3_ (dst, src1, src2); 471 return BITSET_AND_CMP_ (dst->s.bset, src1->s.bset, src2->s.bset); 476 bitset_stats_andn (bitset dst, bitset src1, bitset src2) argument 478 BITSET_CHECK3_ (dst, src1, src2); 479 BITSET_ANDN_ (dst->s.bset, src1->s.bset, src2->s.bset); 484 bitset_stats_andn_cmp (bitset dst, bitset src1, bitse argument 492 bitset_stats_or(bitset dst, bitset src1, bitset src2) argument 500 bitset_stats_or_cmp(bitset dst, bitset src1, bitset src2) argument 508 bitset_stats_xor(bitset dst, bitset src1, bitset src2) argument 516 bitset_stats_xor_cmp(bitset dst, bitset src1, bitset src2) argument 524 bitset_stats_and_or(bitset dst, bitset src1, bitset src2, bitset src3) argument 532 bitset_stats_and_or_cmp(bitset dst, bitset src1, bitset src2, bitset src3) argument 540 bitset_stats_andn_or(bitset dst, bitset src1, bitset src2, bitset src3) argument 548 bitset_stats_andn_or_cmp(bitset dst, bitset src1, bitset src2, bitset src3) argument 556 bitset_stats_or_and(bitset dst, bitset src1, bitset src2, bitset src3) argument 564 bitset_stats_or_and_cmp(bitset dst, bitset src1, bitset src2, bitset src3) argument [all...] |
H A D | bitset.c | 409 bitset_op4_cmp (bitset dst, bitset src1, bitset src2, bitset src3, argument 428 bitset_or (tmp, src1, src2); 433 bitset_and (tmp, src1, src2); 438 bitset_andn (tmp, src1, src2); 450 bitset_and_or_ (bitset dst, bitset src1, bitset src2, bitset src3) argument 452 bitset_and_or_cmp_ (dst, src1, src2, src3); 459 bitset_and_or_cmp_ (bitset dst, bitset src1, bitset src2, bitset src3) argument 461 return bitset_op4_cmp (dst, src1, src2, src3, BITSET_OP_AND_OR); 467 bitset_andn_or_ (bitset dst, bitset src1, bitset src2, bitset src3) argument 469 bitset_andn_or_cmp_ (dst, src1, src 476 bitset_andn_or_cmp_(bitset dst, bitset src1, bitset src2, bitset src3) argument 484 bitset_or_and_(bitset dst, bitset src1, bitset src2, bitset src3) argument 493 bitset_or_and_cmp_(bitset dst, bitset src1, bitset src2, bitset src3) argument [all...] |
H A D | abitset.c | 427 abitset_and (bitset dst, bitset src1, bitset src2) argument 430 bitset_word *src1p = ABITSET_WORDS (src1); 441 abitset_and_cmp (bitset dst, bitset src1, bitset src2) argument 445 bitset_word *src1p = ABITSET_WORDS (src1); 465 abitset_andn (bitset dst, bitset src1, bitset src2) argument 468 bitset_word *src1p = ABITSET_WORDS (src1); 479 abitset_andn_cmp (bitset dst, bitset src1, bitset src2) argument 483 bitset_word *src1p = ABITSET_WORDS (src1); 503 abitset_or (bitset dst, bitset src1, bitset src2) argument 506 bitset_word *src1p = ABITSET_WORDS (src1); 517 abitset_or_cmp(bitset dst, bitset src1, bitset src2) argument 541 abitset_xor(bitset dst, bitset src1, bitset src2) argument 555 abitset_xor_cmp(bitset dst, bitset src1, bitset src2) argument 579 abitset_and_or(bitset dst, bitset src1, bitset src2, bitset src3) argument 594 abitset_and_or_cmp(bitset dst, bitset src1, bitset src2, bitset src3) argument 619 abitset_andn_or(bitset dst, bitset src1, bitset src2, bitset src3) argument 634 abitset_andn_or_cmp(bitset dst, bitset src1, bitset src2, bitset src3) argument 659 abitset_or_and(bitset dst, bitset src1, bitset src2, bitset src3) argument 674 abitset_or_and_cmp(bitset dst, bitset src1, bitset src2, bitset src3) argument [all...] |
/external/opencv/cv/src/ |
H A D | _cvmatrix.h | 63 #define icvAddMatrix_32f( src1, src2, dst, w, h ) \ 64 icvAddVector_32f( (src1), (src2), (dst), (w)*(h)) 66 #define icvSubMatrix_32f( src1, src2, dst, w, h ) \ 67 icvSubVector_32f( (src1), (src2), (dst), (w)*(h)) 91 CV_INLINE double icvDotProduct_32f( const float* src1, const float* src2, int len ) argument 94 for( int i = 0; i < len; i++ ) s += src1[i]*src2[i]; 102 CV_INLINE double icvDotProduct_64f( const double* src1, const double* src2, int len ) argument 105 for( int i = 0; i < len; i++ ) s += src1[i]*src2[i]; 113 CV_INLINE void icvMulVectors_32f( const float* src1, const float* src2, argument 118 dst[i] = src1[ 123 icvMulVectors_64d( const double* src1, const double* src2, double* dst, int len ) argument 134 icvAddVector_32f( const float* src1, const float* src2, float* dst, int len ) argument 144 icvAddVector_64d( const double* src1, const double* src2, double* dst, int len ) argument 155 icvSubVector_32f( const float* src1, const float* src2, float* dst, int len ) argument 165 icvSubVector_64d( const double* src1, const double* src2, double* dst, int len ) argument 283 icvMulMatrix_32f( const float* src1, int w1, int h1, const float* src2, int w2, int h2, float* dst ) argument 308 icvMulMatrix_64d( const double* src1, int w1, int h1, const double* src2, int w2, int h2, double* dst ) argument [all...] |
H A D | cvderiv.cpp | 575 const int *src0 = src[-1], *src1 = src[0], *src2 = src[1]; local 580 int s0 = src0[i] - src1[i]*2 + src2[i] + src1[i+width]; 581 int s1 = src0[i+1] - src1[i+1]*2 + src2[i+1] + src1[i+width+1]; 586 dst[i] = (short)(src0[i] - src1[i]*2 + src2[i] + src1[i+width]); 591 int s0 = src0[i] - src1[i]*2 + src2[i] + 592 src0[i+width] + src1[i+width]*2 + src2[i+width]; 593 int s1 = src0[i+1] - src1[ 609 const int *src0 = src[-2], *src1 = src[-1], *src2 = src[0], *src3 = src[1], *src4 = src[2]; local 643 const int* src1 = src[k] + i, *src2 = src[-k] + i; local 659 const int* src1 = src[k] + i, *src2 = src[-k] + i; local 675 const int* src1 = src[k] + i, *src2 = src[-k] + i; local 717 const float *src0 = src[-1], *src1 = src[0], *src2 = src[1]; local 751 const float *src0 = src[-2], *src1 = src[-1], *src2 = src[0], *src3 = src[1], *src4 = src[2]; local 772 const float* src1 = src[k] + i, *src2 = src[-k] + i; local 788 const float* src1 = src[k] + i, *src2 = src[-k] + i; local [all...] |
/external/clang/test/CodeGenCXX/ |
H A D | debug-info-line.cpp | 86 int *src1(); 90 src1())[src2()]; 95 int src1[1]; local 99 src1)[src2()]; 104 int src1[1][i]; local 108 src1)[src2()];
|
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_vec4.h | 164 src_reg src1 = src_reg(), 339 src_reg src0, src_reg src1); 342 src_reg src0, src_reg src1, src_reg src2); 353 vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1); 354 vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1); 355 vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1); 356 vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1); 357 vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1); 358 vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1); 359 vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1); [all...] |
/external/mesa3d/src/gallium/auxiliary/tgsi/ |
H A D | tgsi_exec.c | 115 const union tgsi_exec_channel *src1, 118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0]; 119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1]; 120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2]; 121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3]; 127 const union tgsi_exec_channel *src1, 113 micro_clamp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument 125 micro_cmp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument 137 micro_cnd(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument 270 micro_lrp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument 282 micro_mad(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument 346 micro_seq(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 357 micro_sge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 388 micro_sgt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 409 micro_sle(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 420 micro_slt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 431 micro_sne(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 891 micro_add(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 956 micro_lt( union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2, const union tgsi_exec_channel *src3 ) argument 970 micro_max(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 981 micro_min(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 992 micro_mul(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 1033 micro_sub(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3140 micro_shl(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3151 micro_and(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3162 micro_or(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3173 micro_xor(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3184 micro_mod(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3205 micro_idiv(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3216 micro_imax(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3227 micro_imin(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3238 micro_isge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3249 micro_ishr(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3260 micro_islt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3291 micro_uadd(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3302 micro_udiv(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3313 micro_umad(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument 3325 micro_umax(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3336 micro_umin(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3347 micro_umod(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3358 micro_umul(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3369 micro_useq(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3380 micro_usge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3391 micro_ushr(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3402 micro_uslt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3413 micro_usne(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument 3434 micro_ucmp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument [all...] |
/external/pdfium/core/src/fxcodec/jbig2/ |
H A D | JBig2_Image.cpp | 202 FX_DWORD src0, src1, src, dest, s1, s2, m1, m2, m3; local 375 src1 = *srcPtr++; 377 dest |= src1 >> s1; 382 src0 = src1; 383 src1 = *srcPtr++; 384 src = (((src0 << 8) | src1) >> s1) & 0xff; 389 src0 = src1; 391 src1 = *srcPtr++; 393 src1 = 0; 395 src = (((src0 << 8) | src1) >> s [all...] |
/external/vixl/src/vixl/a64/ |
H A D | logic-a64.cc | 702 const LogicVRegister& src1, 707 int64_t sa = src1.Int(vform, i); 709 uint64_t ua = src1.Uint(vform, i); 730 const LogicVRegister& src1, 735 return cmp(vform, dst, src1, imm_reg, cond); 741 const LogicVRegister& src1, 745 uint64_t ua = src1.Uint(vform, i); 755 const LogicVRegister& src1, 761 uint64_t ua = src1.UintLeftJustified(vform, i); 769 int64_t sa = src1 700 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 728 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, int imm, Condition cond) argument 739 cmptst(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 753 add(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 784 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 796 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 807 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 818 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 830 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 841 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 852 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 863 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 875 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 887 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 899 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 911 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 923 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 935 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 947 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 959 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 971 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 983 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 995 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1007 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1019 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1031 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1043 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1055 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1067 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1079 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1090 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1113 pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1126 pmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1140 pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1155 sub(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1182 and_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1194 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1206 orn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1218 eor(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1230 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1259 bif(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1275 bit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1291 bsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1307 sminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument 1328 smax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1336 smin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1364 smaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1375 sminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1486 uminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument 1507 umax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1515 umin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1543 umaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1554 uminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1873 sshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1919 ushl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2136 absdiff(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool issigned) argument 2157 saba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2169 uaba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2328 ext(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 2781 uaddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2793 uaddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2805 uaddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2816 uaddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2827 saddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2839 saddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2851 saddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2862 saddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2873 usubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2885 usubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2897 usubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2908 usubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2919 ssubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2931 ssubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2943 ssubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2954 ssubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2965 uabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2977 uabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2989 sabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3001 sabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3013 uabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3025 uabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3037 sabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3049 sabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3061 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3073 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3085 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3097 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3109 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3121 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3133 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3145 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3157 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3169 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3181 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3193 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3205 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3215 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3225 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3235 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3245 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3255 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3265 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool round) argument 3295 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3303 addhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3308 add(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3314 addhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3325 raddhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3330 add(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3336 raddhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3347 subhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3352 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3358 subhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3369 rsubhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3374 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3380 rsubhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3391 trn1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3411 trn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3431 zip1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3451 zip2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3471 uzp1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3490 uzp2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3899 fnmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3910 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3925 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3940 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3955 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3970 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 3997 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 4030 fabscmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 4051 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4067 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4082 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4098 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4168 fabd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4272 fmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 4292 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 4312 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 4332 fmulx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument [all...] |
H A D | simulator-a64.h | 1389 int64_t src1, 1538 const LogicVRegister& src1, 1543 const LogicVRegister& src1, 1548 const LogicVRegister& src1, 1552 const LogicVRegister& src1, 1556 const LogicVRegister& src1, 1560 const LogicVRegister& src1, 1564 const LogicVRegister& src1, 1568 const LogicVRegister& src1, 1572 const LogicVRegister& src1, [all...] |
/external/libmpeg2/common/x86/ |
H A D | impeg2_inter_pred_sse42_intr.c | 225 UWORD8 *src1, *src2; local 233 src1 = buf_src1->pu1_y; 237 src1_r0 = _mm_loadu_si128((__m128i *) (src1)); 238 src1_r1 = _mm_loadu_si128((__m128i *) (src1 + 16)); 239 src1_r2 = _mm_loadu_si128((__m128i *) (src1 + 2 * 16)); 240 src1_r3 = _mm_loadu_si128((__m128i *) (src1 + 3 * 16)); 258 src1 += 4 * 16; 261 src1_r0 = _mm_loadu_si128((__m128i *) (src1)); 262 src1_r1 = _mm_loadu_si128((__m128i *) (src1 + 16)); 263 src1_r2 = _mm_loadu_si128((__m128i *) (src1 [all...] |