Searched refs:v16i1 (Results 1 - 7 of 7) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h62 v16i1 = 16, // 16 x i1 enumerator in enum:llvm::MVT::SimpleValueType
205 SimpleTy == MVT::v16i1);
287 case v16i1 :
337 case v16i1:
400 case v16i1:
530 if (NumElements == 16) return MVT::v16i1;
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp359 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 * AmortizationCost },
361 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 * AmortizationCost },
364 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost }
/external/llvm/lib/IR/
H A DValueTypes.cpp134 case MVT::v16i1: return "v16i1";
202 case MVT::v16i1: return VectorType::get(Type::getInt1Ty(Context), 16);
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp277 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
279 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
282 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp508 // v16i1 -> v16i32 - load + broadcast
509 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
510 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
519 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
H A DX86ISelLowering.cpp1250 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1264 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1298 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1311 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1336 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1338 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1344 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1345 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1348 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1609 case 16: return MVT::v16i1;
[all...]
/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp76 case MVT::v16i1: return "MVT::v16i1";

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