Searched refs:v4f32 (Results 1 - 25 of 30) sorted by relevance

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/external/clang/test/CodeGen/
H A Dvectorcall.c56 typedef float __attribute__((vector_size(16))) v4f32; typedef
57 struct HVA2 { v4f32 x, y; };
58 struct HVA4 { v4f32 w, x, y, z; };
64 void __vectorcall hva2(struct HVA4 a, struct HVA4 b, v4f32 c) {}
68 void __vectorcall hva3(v4f32 a, v4f32 b, v4f32 c, v4f32 d, v4f32 e, struct HVA2 f) {}
H A Dsystemz-abi-vector.c27 typedef __attribute__((vector_size(16))) float v4f32; typedef
87 v4f32 pass_v4f32(v4f32 arg) { return arg; }
H A Dx86_64-arguments.c155 typedef float v4f32 __attribute__((__vector_size__(16))); typedef
156 v4f32 f25(v4f32 X) {
179 v4f32 v;
H A Dbuiltins-mips-msa.c14 typedef float v4f32 __attribute__ ((vector_size(16))); typedef
47 v4f32 v4f32_a = (v4f32) {0.5, 1, 2, 3};
48 v4f32 v4f32_b = (v4f32) {1.5, 2, 3, 4};
49 v4f32 v4f32_r;
/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp359 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
396 // nodes. A v4i32/v4f32 BLENDI generates a single 'blendps'/'blendpd'.
398 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1},
421 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
438 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, // shufps + pshufd
478 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
479 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 },
480 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
481 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
482 { ISD::SINT_TO_FP, MVT::v4f32, MV
[all...]
H A DX86ISelLowering.cpp778 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
780 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
781 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
782 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
783 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
785 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
786 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
787 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
788 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custo
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
196 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
207 // Complex: to v4f32
208 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
209 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
210 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
211 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
224 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
227 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
238 // Complex, from v4f32
[all...]
H A DAArch64ISelDAGToDAG.cpp2268 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2286 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2304 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2322 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2340 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2358 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2376 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2394 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2412 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2425 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
[all...]
H A DAArch64ISelLowering.cpp112 addQRTypeForNEON(MVT::v4f32);
318 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
326 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
327 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
328 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
329 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
330 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
331 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
572 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
606 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MV
[all...]
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp59 { ISD::FP_EXTEND, MVT::v4f32, 4 }
105 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
106 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
114 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
115 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
116 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
117 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
118 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
119 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
129 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32,
[all...]
H A DARMISelLowering.cpp436 addQRTypeForNEON(MVT::v4f32);
445 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
446 // supported for v4f32.
482 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
483 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
484 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
485 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
486 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
487 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
488 setOperationAction(ISD::FLOG2, MVT::v4f32, Expan
[all...]
H A DARMISelDAGToDAG.cpp1801 case MVT::v4f32:
1938 case MVT::v4f32:
2099 case MVT::v4f32:
2751 case MVT::v4f32:
2771 case MVT::v4f32:
2790 case MVT::v4f32:
/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h98 v4f32 = 47, // 4 x f32 enumerator in enum:llvm::MVT::SimpleValueType
227 SimpleTy == MVT::v8f16 || SimpleTy == MVT::v4f32 ||
318 case v4f32:
357 case v4f32:
431 case v4f32:
573 if (NumElements == 4) return MVT::v4f32;
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp501 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
502 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
503 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
504 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
506 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
511 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
512 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
515 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
516 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
528 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custo
[all...]
H A DPPCISelDAGToDAG.cpp2091 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32).
2120 if (VecVT == MVT::v4f32)
2127 if (VecVT == MVT::v4f32)
2134 if (VecVT == MVT::v4f32)
2475 case MVT::v4f32: Opcode = PPC::QVLFSUX; break; // QPX
2722 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600GenRegisterInfo.pl97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
H A DAMDILISelLowering.cpp61 (int)MVT::v4f32,
89 (int)MVT::v4f32,
505 FLTTY = MVT::v4f32;
H A DR600ISelLowering.cpp30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
H A DSIISelLowering.cpp30 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp160 DecodeBLENDMask(MVT::v4f32,
263 DecodeMOVSLDUPMask(MVT::v4f32, ShuffleMask);
289 DecodeMOVSHDUPMask(MVT::v4f32, ShuffleMask);
652 DecodeSHUFPMask(MVT::v4f32,
702 DecodeUNPCKLMask(MVT::v4f32, ShuffleMask);
754 DecodeUNPCKHMask(MVT::v4f32, ShuffleMask);
779 DecodePSHUFMask(MVT::v4f32,
857 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
/external/llvm/lib/IR/
H A DValueTypes.cpp165 case MVT::v4f32: return "v4f32";
233 case MVT::v4f32: return VectorType::get(Type::getFloatTy(Context), 4);
/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp212 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
253 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp153 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
356 MVT::v2f32, MVT::v4f32
H A DR600ISelLowering.cpp36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
153 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
158 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
658 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
773 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
1534 // non-constant ptr can't be folded, keeps it as a v4f32 load
/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp107 case MVT::v4f32: return "MVT::v4f32";

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