| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineValueType.h | 87 v8i64 = 40, // 8 x i64 enumerator in enum:llvm::MVT::SimpleValueType
242 SimpleTy == MVT::v8i64 || SimpleTy == MVT::v16i32);
311 case v8i64:
347 case v8i64:
442 case v8i64:
562 if (NumElements == 8) return MVT::v8i64;
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 131 { ISD::SHL, MVT::v8i64, 1 },
132 { ISD::SRL, MVT::v8i64, 1 },
133 { ISD::SRA, MVT::v8i64, 1 },
504 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 },
505 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 },
506 { ISD::TRUNCATE, MVT::v16i32, MVT::v8i64, 4 },
516 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i32, 3 },
517 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i32, 3 },
565 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
598 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64,
[all...] |
| H A D | X86ISelLowering.cpp | 1245 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1262 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1314 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1316 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1333 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1341 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1350 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1353 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1356 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1361 setOperationAction(ISD::SRL, MVT::v8i64, Custo
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 93 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
94 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
95 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
96 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
281 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
|
| H A D | ARMISelDAGToDAG.cpp | 2021 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2142 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
|
| H A D | ARMISelLowering.cpp | 999 case MVT::v8i64:
1150 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1155 if (VT == MVT::v8i64)
|
| /external/llvm/lib/IR/ |
| H A D | ValueTypes.cpp | 158 case MVT::v8i64: return "v8i64";
226 case MVT::v8i64: return VectorType::get(Type::getInt64Ty(Context), 8);
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 363 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
|
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 100 case MVT::v8i64: return "MVT::v8i64";
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| H A D | X86InstComments.cpp | 528 DecodeUNPCKHMask(MVT::v8i64, ShuffleMask);
617 DecodeUNPCKLMask(MVT::v8i64, ShuffleMask);
|