| /art/runtime/arch/x86_64/ |
| H A D | quick_entrypoints_x86_64.S | 499 andl LITERAL(0xFFFFFFF0), %edx // Align frame size to 16 bytes.
593 andl LITERAL(0xFFFFFFF0), %edx // Align frame size to 16 bytes.
936 andl LITERAL(OBJECT_ALIGNMENT_MASK_TOGGLED), %ecx
1049 andl LITERAL(LOCK_WORD_READ_BARRIER_STATE_MASK_TOGGLED), %ecx // zero the read barrier bits.
1064 andl LITERAL(LOCK_WORD_READ_BARRIER_STATE_MASK_TOGGLED), %ecx // zero the read barrier bits.
1093 andl LITERAL(LOCK_WORD_READ_BARRIER_STATE_MASK_TOGGLED), %edx // zero the read barrier bits.
1098 andl LITERAL(LOCK_WORD_READ_BARRIER_STATE_MASK), %ecx // ecx: new lock word zero except original rb bits.
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| /art/runtime/arch/x86/ |
| H A D | quick_entrypoints_x86.S | 441 andl LITERAL(0xFFFFFFF0), %ebx
538 andl LITERAL(0xFFFFFFF0), %ebx
990 andl LITERAL(LOCK_WORD_READ_BARRIER_STATE_MASK_TOGGLED), %ecx // zero the read barrier bits.
1006 andl LITERAL(LOCK_WORD_READ_BARRIER_STATE_MASK_TOGGLED), %ecx // zero the read barrier bits.
1046 andl LITERAL(LOCK_WORD_READ_BARRIER_STATE_MASK_TOGGLED), %edx // zero the read barrier bits.
1052 andl LITERAL(LOCK_WORD_READ_BARRIER_STATE_MASK), %ecx // ecx: new lock word zero except original rb bits.
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| /art/compiler/utils/x86/ |
| H A D | assembler_x86.h | 378 void andl(Register dst, const Immediate& imm);
379 void andl(Register dst, Register src);
380 void andl(Register dst, const Address& address);
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| H A D | assembler_x86.cc | 1050 void X86Assembler::andl(Register dst, Register src) { function in class:art::x86::X86Assembler
1057 void X86Assembler::andl(Register reg, const Address& address) { function in class:art::x86::X86Assembler
1064 void X86Assembler::andl(Register dst, const Immediate& imm) { function in class:art::x86::X86Assembler
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| /art/compiler/utils/x86_64/ |
| H A D | assembler_x86_64.h | 495 void andl(CpuRegister dst, const Immediate& imm);
496 void andl(CpuRegister dst, CpuRegister src);
497 void andl(CpuRegister reg, const Address& address);
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| H A D | assembler_x86_64_test.cc | 547 DriverStr(Repeatrr(&x86_64::X86_64Assembler::andl, "andl %{reg2}, %{reg1}"), "andl");
551 DriverStr(Repeatri(&x86_64::X86_64Assembler::andl, 4U, "andl ${imm}, %{reg}"), "andli");
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| H A D | assembler_x86_64.cc | 1351 void X86_64Assembler::andl(CpuRegister dst, CpuRegister src) { function in class:art::x86_64::X86_64Assembler
1359 void X86_64Assembler::andl(CpuRegister reg, const Address& address) { function in class:art::x86_64::X86_64Assembler
1367 void X86_64Assembler::andl(CpuRegister dst, const Immediate& imm) { function in class:art::x86_64::X86_64Assembler
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| /art/compiler/optimizing/ |
| H A D | code_generator_x86.cc | 2307 __ andl(EAX, Immediate(kC2ConditionMask));
4520 __ andl(first.AsRegister<Register>(), second.AsRegister<Register>());
4529 __ andl(first.AsRegister<Register>(),
4541 __ andl(first.AsRegister<Register>(), Address(ESP, second.GetStackIndex()));
4553 __ andl(first.AsRegisterPairLow<Register>(), second.AsRegisterPairLow<Register>());
4554 __ andl(first.AsRegisterPairHigh<Register>(), second.AsRegisterPairHigh<Register>());
4565 __ andl(first.AsRegisterPairLow<Register>(), Address(ESP, second.GetStackIndex()));
4566 __ andl(first.AsRegisterPairHigh<Register>(),
4591 __ andl(first_low, low);
4596 __ andl(first_hig
[all...] |
| H A D | intrinsics_x86_64.cc | 320 // __ andl(Address(CpuRegister(RSP), output.GetStackIndex()), Immediate(INT64_C(0x7FFFFFFF)));
1512 __ andl(temp, imm_mask);
1513 __ andl(reg, imm_mask);
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| H A D | intrinsics_x86.cc | 370 // __ andl(Address(Register(RSP), output.GetHighStackIndex(kX86WordSize)),
375 // __ andl(Address(Register(RSP), output.GetStackIndex()), Immediate(0x7FFFFFFF));
1649 __ andl(temp, imm_mask);
1650 __ andl(reg, imm_mask);
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| H A D | code_generator_x86_64.cc | 2436 __ andl(CpuRegister(RAX), Immediate(kC2ConditionMask));
4358 __ andl(first.AsRegister<CpuRegister>(), second.AsRegister<CpuRegister>());
4368 __ andl(first.AsRegister<CpuRegister>(), imm);
4378 __ andl(first.AsRegister<CpuRegister>(), address);
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