Searched refs:andq (Results 1 - 5 of 5) sorted by relevance
/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64.h | 498 void andq(CpuRegister dst, const Immediate& imm); 499 void andq(CpuRegister dst, CpuRegister src); 500 void andq(CpuRegister reg, const Address& address);
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H A D | assembler_x86_64_test.cc | 538 DriverStr(RepeatRR(&x86_64::X86_64Assembler::andq, "andq %{reg2}, %{reg1}"), "andq"); 542 DriverStr(RepeatRI(&x86_64::X86_64Assembler::andq, 4U /* andq only supports 32b imm */, 543 "andq ${imm}, %{reg}"), "andqi"); 779 GetAssembler()->andq(x86_64::CpuRegister(x86_64::R9), 781 const char* expected = "andq 0(%RAX), %r9\n"; 782 DriverStr(expected, "andq");
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H A D | assembler_x86_64.cc | 1374 void X86_64Assembler::andq(CpuRegister reg, const Immediate& imm) { function in class:art::x86_64::X86_64Assembler 1376 CHECK(imm.is_int32()); // andq only supports 32b immediate. 1382 void X86_64Assembler::andq(CpuRegister dst, CpuRegister src) { function in class:art::x86_64::X86_64Assembler 1390 void X86_64Assembler::andq(CpuRegister dst, const Address& src) { function in class:art::x86_64::X86_64Assembler
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/art/compiler/optimizing/ |
H A D | intrinsics_x86_64.cc | 316 // __ andq(Address(CpuRegister(RSP), output.GetStackIndex()), cpu_temp); 1557 __ andq(temp, temp_mask); 1558 __ andq(reg, temp_mask);
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H A D | code_generator_x86_64.cc | 4400 __ andq(first_reg, Immediate(static_cast<int32_t>(value))); 4402 __ andq(first_reg, codegen_->LiteralInt64Address(value)); 4405 __ andq(first_reg, Address(CpuRegister(RSP), second.GetStackIndex())); 4407 __ andq(first_reg, second.AsRegister<CpuRegister>());
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