Searched refs:base_reg (Results 1 - 8 of 8) sorted by relevance

/art/compiler/dex/quick/arm/
H A Dassemble_arm.cc1318 int base_reg = ((lir->opcode == kThumb2LdrdPcRel8) || local
1324 base_reg, 0, 0, 0, 0, lir->target);
1347 lir->operands[2] = base_reg;
1350 lir->operands[1] = base_reg;
/art/compiler/dex/quick/x86/
H A Dutility_x86.cc945 LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, argument
948 LIR* inst = NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg.GetReg(),
H A Dcodegen_x86.h808 * @param base_reg The register holding the base address.
814 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
/art/compiler/dex/quick/
H A Dcodegen_util.cc1257 LIR *Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, argument
1260 LIR* inst = Load32Disp(base_reg, offset, temp_reg);
H A Dmir_to_lir.h1129 * @param base_reg The register holding the base address.
1136 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
/art/compiler/dex/quick/arm64/
H A Dcodegen_arm64.h85 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
H A Dint_arm64.cc301 RegStorage base_reg, int offset, int check_value,
309 Load32Disp(base_reg, offset, temp_reg);
300 OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, int offset, int check_value, LIR* target, LIR** compare) argument
/art/compiler/dex/
H A Dlocal_value_numbering.cc1333 int base_reg = (opcode == Instruction::IPUT_WIDE) ? 2 : 1; local
1334 uint16_t base = GetOperandValue(mir->ssa_rep->uses[base_reg]);

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