Searched refs:disp (Results 1 - 20 of 20) sorted by relevance

/art/runtime/arch/mips/
H A Dasm_support_mips.S74 from unaligned (mod-4-aligned) mem location disp(base) */
75 .macro LDu feven,fodd,disp,base,temp
76 l.s \feven, \disp(\base)
77 lw \temp, \disp+4(\base)
82 to unaligned (mod-4-aligned) mem location disp(base) */
83 .macro SDu feven,fodd,disp,base,temp
85 s.s \feven, \disp(\base)
86 sw \temp, \disp+4(\base)
101 .macro LDu feven,fodd,disp,base,temp
102 l.s \feven, \disp(\bas
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/art/compiler/utils/x86/
H A Dassembler_x86.h104 void SetDisp8(int8_t disp) { argument
106 encoding_[length_++] = static_cast<uint8_t>(disp);
109 void SetDisp32(int32_t disp) { argument
111 int disp_size = sizeof(disp);
112 memmove(&encoding_[length_], &disp, disp_size);
135 Address(Register base_in, int32_t disp) { argument
136 Init(base_in, disp);
139 Address(Register base_in, Offset disp) { argument
140 Init(base_in, disp.Int32Value());
143 Address(Register base_in, FrameOffset disp) { argument
148 Address(Register base_in, MemberOffset disp) argument
152 Init(Register base_in, int32_t disp) argument
167 Address(Register index_in, ScaleFactor scale_in, int32_t disp) argument
174 Address(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp) argument
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/art/compiler/dex/quick/x86/
H A Dcodegen_x86.h302 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
446 void EmitDisp(uint8_t base, int32_t disp);
448 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp);
450 int32_t disp);
455 void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp);
457 int32_t disp);
458 void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg);
459 void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp);
461 int32_t raw_index, int scale, int32_t disp);
463 int32_t disp, int32_
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H A Dassemble_x86.cc725 case kMem: // lir operands - 0: base, 1: disp
727 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp
729 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg
731 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate
733 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
736 case kThreadReg: // lir operands - 0: disp, 1: reg
743 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp
745 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
748 case kRegThread: // lir operands - 0: reg, 1: disp
760 case kMemImm: // lir operands - 0: base, 1: disp,
876 ModrmForDisp(int base, int disp) argument
999 EmitDisp(uint8_t base, int32_t disp) argument
1026 EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp) argument
1048 EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int32_t disp) argument
1128 EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) argument
1141 EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, int32_t disp) argument
1152 EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg) argument
1164 EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp) argument
1170 EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t raw_index, int scale, int32_t disp) argument
1183 EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, int32_t disp, int32_t raw_reg) argument
1189 EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm) argument
1199 EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, int32_t disp, int32_t imm) argument
1211 EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp) argument
1254 EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) argument
1267 EmitMemRegImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) argument
1287 EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) argument
1392 EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm) argument
1431 EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc) argument
1481 EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, int32_t cc) argument
1546 EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) argument
1555 EmitCallImmediate(const X86EncodingMap* entry, int32_t disp) argument
1566 EmitCallThread(const X86EncodingMap* entry, int32_t disp) argument
1581 int disp; local
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H A Dutility_x86.cc462 0 /* scale */, 0 /* disp */);
466 0 /* scale */, 0 /* disp */);
517 // TODO: fix bug in LEA encoding when disp == 0
519 r_src.GetReg() /* index */, value /* scale */, 0 /* disp */);
523 0 /* scale */, value /* disp */);
556 LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { argument
564 return NewLIR2(opcode, r_base.GetReg(), disp);
/art/compiler/utils/x86_64/
H A Dassembler_x86_64.h132 void SetDisp8(int8_t disp) { argument
134 encoding_[length_++] = static_cast<uint8_t>(disp);
137 void SetDisp32(int32_t disp) { argument
139 int disp_size = sizeof(disp);
140 memmove(&encoding_[length_], &disp, disp_size);
169 Address(CpuRegister base_in, int32_t disp) { argument
170 Init(base_in, disp);
173 Address(CpuRegister base_in, Offset disp) { argument
174 Init(base_in, disp.Int32Value());
177 Address(CpuRegister base_in, FrameOffset disp) { argument
182 Address(CpuRegister base_in, MemberOffset disp) argument
186 Init(CpuRegister base_in, int32_t disp) argument
208 Address(CpuRegister index_in, ScaleFactor scale_in, int32_t disp) argument
215 Address(CpuRegister base_in, CpuRegister index_in, ScaleFactor scale_in, int32_t disp) argument
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/art/compiler/linker/arm64/
H A Drelative_patcher_arm64_test.cc159 uint32_t disp = target_offset - (adrp_offset & ~0xfffu); local
160 DCHECK_EQ(disp & 3u, 0u);
162 ((disp & 0xfffu) << (10 - 2)); // imm12 = ((disp & 0xfffu) >> 2) is at bit 10.
164 ((disp & 0x3000u) << (29 - 12)) | // immlo = ((disp & 0x3000u) >> 12) is at bit 29,
165 ((disp & 0xffffc000) >> (14 - 5)) | // immhi = (disp >> 14) is at bit 5,
166 // We take the sign bit from the disp, limiting disp t
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H A Drelative_patcher_arm64.cc160 uint32_t disp = target_offset - ((patch_offset - literal_offset + pc_insn_offset) & ~0xfffu); local
194 insn = PatchAdrp(insn, disp);
222 uint32_t imm12 = (disp & 0xfffu) >> shift;
243 uint32_t Arm64RelativePatcher::PatchAdrp(uint32_t adrp, uint32_t disp) { argument
246 ((disp & 0x00003000u) << (29 - 12)) |
248 ((disp & 0xffffc000u) >> (12 + 2 - 5)) |
254 ((disp & 0x80000000u) >> (31 - 23));
H A Drelative_patcher_arm64.h42 static uint32_t PatchAdrp(uint32_t adrp, uint32_t disp);
/art/compiler/dex/quick/
H A Dcodegen_util.cc569 int disp = boundary_lir->offset - bx_offset; local
571 Push32(&code_buffer_, disp);
574 << std::hex << key << ", disp: 0x"
575 << std::hex << disp; local
594 int disp = boundary_lir->offset - bx_offset; local
595 Push32(&code_buffer_, disp);
597 LOG(INFO) << " Case[" << elems << "] disp: 0x"
598 << std::hex << disp; local
H A Dgen_invoke.cc623 int32_t disp; local
625 disp = GetThreadOffset<8>(trampoline).Int32Value();
627 disp = GetThreadOffset<4>(trampoline).Int32Value();
629 cg->LoadWordDisp(cg->TargetPtrReg(kSelf), disp, cg->TargetPtrReg(kInvokeTgt));
H A Dmir_to_lir.h1414 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0;
/art/compiler/dex/quick/arm/
H A Dcodegen_arm.h206 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
H A Dutility_arm.cc1246 LIR* ArmMir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { argument
1247 UNUSED(op, r_base, disp);
H A Dassemble_arm.cc1512 int32_t disp = target_disp - ((lir->offset + 4) & ~3); local
1513 if (disp < 4096) {
1514 lir->operands[1] = disp;
1559 // operands[1] should hold disp, [2] has add, [3] has tab_rec
1569 // operands[1] should hold disp, [2] has add, [3] has tab_rec
/art/compiler/dex/quick/mips/
H A Dcodegen_mips.h203 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
H A Dutility_mips.cc1034 LIR* MipsMir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { argument
1035 UNUSED(op, r_base, disp);
/art/compiler/dex/quick/arm64/
H A Dutility_arm64.cc1390 LIR* Arm64Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { argument
1391 UNUSED(op, r_base, disp);
H A Dcodegen_arm64.h209 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
/art/runtime/interpreter/
H A Dinterpreter_goto_table_impl.cc37 int32_t disp = static_cast<int32_t>(_offset); \
38 inst = inst->RelativeAt(disp); \
39 dex_pc = static_cast<uint32_t>(static_cast<int32_t>(dex_pc) + disp); \

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