/art/compiler/dex/ |
H A D | local_value_numbering.h | 55 uint16_t GetSregValue(uint16_t s_reg) const { 56 DCHECK(!gvn_->GetMirGraph()->GetRegLocation(s_reg).wide); 57 return GetSregValueImpl(s_reg, &sreg_value_map_); 60 uint16_t GetSregValueWide(uint16_t s_reg) const { 61 DCHECK(gvn_->GetMirGraph()->GetRegLocation(s_reg).wide); 62 return GetSregValueImpl(s_reg, &sreg_wide_value_map_); 91 // Key is s_reg, value is value name. 97 uint16_t GetSregValueImpl(int s_reg, const SregValueMap* map) const { argument 99 auto lb = map->find(s_reg); 103 res = gvn_->FindValue(kNoValue, s_reg, kNoValu 108 SetOperandValueImpl(uint16_t s_reg, uint16_t value, SregValueMap* map) argument 113 GetOperandValueImpl(int s_reg, const SregValueMap* map) const argument 125 SetOperandValue(uint16_t s_reg, uint16_t value) argument 137 SetOperandValueWide(uint16_t s_reg, uint16_t value) argument [all...] |
H A D | type_inference.cc | 168 int32_t s_reg = check_cast->ssa_rep->uses[0]; local 169 auto lb = split_sreg_data_.lower_bound(s_reg); 170 if (lb == split_sreg_data_.end() || split_sreg_data_.key_comp()(s_reg, lb->first)) { 181 split_s_reg_data.ending_mod_s_reg[def_bb->id] = s_reg; 183 lb = split_sreg_data_.PutBefore(lb, s_reg, split_s_reg_data); 212 int32_t s_reg = entry.first; local 213 int v_reg = mir_graph_->SRegToVReg(s_reg); 219 if (IsSRegLiveAtStart(phi_bb, v_reg, s_reg)) { 227 // SSA rename for s_reg. 238 if (IsSRegLiveAtStart(bb, v_reg, s_reg)) { 325 GetSplitSRegData(int32_t s_reg) argument 333 int32_t s_reg = check_cast->ssa_rep->uses[0]; local 373 IsSRegLiveAtStart(BasicBlock* bb, int v_reg, int32_t s_reg) argument 979 int32_t s_reg = defs[0]; local 1041 ModifiedSReg(int32_t s_reg) argument 1052 PhiInputModifiedSReg(int32_t s_reg, BasicBlock* bb, size_t pred_idx) argument [all...] |
H A D | gvn_dead_code_elimination.h | 113 bool IsSRegUsed(uint16_t first_change, uint16_t last_change, int s_reg) const; 134 MIR* CreatePhi(int s_reg);
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H A D | type_inference.h | 388 SplitSRegData* GetSplitSRegData(int32_t s_reg); 393 bool IsSRegLiveAtStart(BasicBlock* bb, int v_reg, int32_t s_reg); 422 int32_t ModifiedSReg(int32_t s_reg); 423 int32_t PhiInputModifiedSReg(int32_t s_reg, BasicBlock* bb, size_t pred_idx);
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H A D | global_value_numbering.cc | 179 int s_reg = pred_bb->last_mir_insn->ssa_rep->uses[0]; local 180 if (pred_lvn->GetSregValue(s_reg) != value_name) {
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H A D | gvn_dead_code_elimination.cc | 361 int s_reg) const { 367 if (ssa_rep->uses[i] == s_reg) { 521 MIR* GvnDeadCodeElimination::CreatePhi(int s_reg) { argument 522 int v_reg = mir_graph_->SRegToVReg(s_reg); 533 phi->ssa_rep->defs[0] = s_reg; 1052 int s_reg = mir->ssa_rep->defs[0]; local 1053 uint16_t new_value = wide ? lvn_->GetSregValueWide(s_reg) : lvn_->GetSregValue(s_reg); 1055 int v_reg = mir_graph_->SRegToVReg(s_reg); 1443 int s_reg local [all...] |
H A D | type_inference_test.cc | 545 void ExpectSRegType(int s_reg, const SRegExpectation& expectation, bool check_loc = true) { argument 548 TypeInference::Type type = type_inference_->sregs_[s_reg]; 551 RegLocation loc = cu_.mir_graph->reg_location_[s_reg]; 552 EXPECT_EQ((flags & kExpectWide) != 0u, loc.wide) << s_reg; 553 EXPECT_EQ((flags & kExpectFp) != 0u, loc.fp) << s_reg; 554 EXPECT_EQ((flags & kExpectCore) != 0u, loc.core) << s_reg; 555 EXPECT_EQ((flags & kExpectRef) != 0u, loc.ref) << s_reg; 556 EXPECT_EQ((flags & kExpectHigh) != 0u, loc.high_word) << s_reg; 559 EXPECT_EQ((flags & kExpectWide) != 0u, type.Wide()) << s_reg; 560 EXPECT_EQ((flags & kExpectNarrow) != 0u, type.Narrow()) << s_reg; 591 ExpectCore(int s_reg, bool core) argument 595 ExpectRef(int s_reg, bool ref) argument 599 ExpectArrayDepth(int s_reg, uint32_t array_depth) argument [all...] |
H A D | local_value_numbering.cc | 388 int s_reg = pred_bb->last_mir_insn->ssa_rep->uses[0]; local 389 null_checked_.insert(other.GetOperandValue(s_reg)); 705 int s_reg = least_entries_bb->last_mir_insn->ssa_rep->uses[0]; local 706 uint32_t value_name = least_entries_lvn->GetOperandValue(s_reg); 1177 int s_reg = uses[pos]; local 1179 value_name = wide ? lvn->GetOperandValueWide(s_reg) : lvn->GetOperandValue(s_reg); 1305 // Use result s_reg - will be unique. 1414 // Use result s_reg - will be unique. 1632 // 1 result, treat as unique each time, use result s_reg 1987 int s_reg = bb->data_flow_info->vreg_to_ssa_map_exit[v_reg]; local [all...] |
H A D | mir_graph.h | 783 bool IsConst(int32_t s_reg) const { 784 return is_constant_v_->IsBitSet(s_reg); 796 int32_t ConstantValue(int32_t s_reg) const { 797 DCHECK(IsConst(s_reg)); 798 return constant_values_[s_reg]; 1317 int GetSSAUseCount(int s_reg);
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H A D | mir_dataflow.cc | 1407 int s_reg = mir->ssa_rep->uses[i]; local 1408 raw_use_counts_[s_reg] += 1u; 1409 use_counts_[s_reg] += weight;
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H A D | mir_optimization.cc | 244 int MIRGraph::GetSSAUseCount(int s_reg) { argument 245 DCHECK_LT(static_cast<size_t>(s_reg), ssa_subscripts_.size()); 246 return raw_use_counts_[s_reg];
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H A D | gvn_dead_code_elimination_test.cc | 238 int SRegToVReg(int32_t s_reg, bool wide) { argument 239 int v_reg = cu_.mir_graph->SRegToVReg(s_reg); 616 // Check that the IGET uses the s_reg 0, v_reg 0, defined by mirs_[0]. 658 // Check that the IGET uses the s_reg 0, v_reg 0, defined by mirs_[0]. 699 // Check that the NEW_INSTANCE defines the s_reg 2, v_reg 2, originally defined by the move. 703 // Check that the first IGET is using the s_reg 2, v_reg 2. 739 // Check that the NEW_INSTANCE defines the s_reg 2, v_reg 2, originally defined by the move 2u. 781 // Check that the NEW_INSTANCE defines the s_reg 4, v_reg 3, originally defined by the move 4u. 812 // Check that the CONST_WIDE defines the s_reg 2, v_reg 1, originally defined by the move 2u. 844 // Check that the CONST defines the s_reg [all...] |
/art/compiler/dex/quick/ |
H A D | ralloc_util.cc | 220 void Mir2Lir::ClobberSReg(int s_reg) { argument 221 if (s_reg != INVALID_SREG) { 222 if (kIsDebugBuild && s_reg == live_sreg_) { 226 if (info->SReg() == s_reg) { 250 int Mir2Lir::SRegToPMap(int s_reg) { argument 251 DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs()); 252 DCHECK_GE(s_reg, 0); 253 int v_reg = mir_graph_->SRegToVReg(s_reg); 258 void Mir2Lir::RecordCorePromotion(RegStorage reg, int s_reg) { argument 259 int p_map_idx = SRegToPMap(s_reg); 272 AllocPreservedCoreReg(int s_reg) argument 290 RecordFpPromotion(RegStorage reg, int s_reg) argument 305 AllocPreservedFpReg(int s_reg) argument 323 AllocPreservedDouble(int s_reg) argument 330 AllocPreservedSingle(int s_reg) argument 460 FindLiveReg(ArenaVector<RegisterInfo*>& regs, int s_reg) argument 471 AllocLiveReg(int s_reg, int reg_class, bool wide) argument 645 NullifyRange(RegStorage reg, int s_reg) argument 808 int s_reg = loc.s_reg_low; local 1495 SRegOffset(int s_reg) argument 1556 LiveOut(int s_reg) argument [all...] |
H A D | mir_to_lir.h | 239 int s_reg; member in struct:art::Mir2Lir::RefCounts 256 * is the low half by looking at the s_reg names. The high s_reg will equal low_sreg + 1. 259 * will be true and partner==self. s_reg refers to the low-order word of the Dalvik 260 * value, and the s_reg of the high word is implied (s_reg + 1). 265 * meaning. If is_temp==true and live==true, wide_value, partner, dirty, s_reg, def_start 267 * the Dalvik value[s] described by s_reg/s_reg+1. 293 * desired s_reg 342 MarkLive(int s_reg) argument [all...] |
/art/compiler/dex/quick/arm/ |
H A D | target_arm.cc | 833 * an even numbered reg. It is possible that the paired s_reg (s_reg+1) 836 * s_reg<=sX[even] & (s_reg+1)<= sX+1. 839 RegStorage ArmMir2Lir::AllocPreservedDouble(int s_reg) { argument 841 int v_reg = mir_graph_->SRegToVReg(s_reg); 842 int p_map_idx = SRegToPMap(s_reg); 888 RegStorage ArmMir2Lir::AllocPreservedSingle(int s_reg) { argument 893 int p_map_idx = SRegToPMap(s_reg); 894 int v_reg = mir_graph_->SRegToVReg(s_reg); [all...] |
H A D | codegen_arm.h | 237 RegStorage AllocPreservedDouble(int s_reg); 238 RegStorage AllocPreservedSingle(int s_reg);
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