Searched refs:shift_amount (Results 1 - 6 of 6) sorted by relevance

/art/compiler/dex/quick/arm/
H A Dint_arm.cc1555 int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; local
1556 if (shift_amount == 0) {
1568 if (shift_amount == 1) {
1571 } else if (shift_amount == 32) {
1574 } else if (shift_amount > 31) {
1575 OpRegRegImm(kOpLsl, rl_result.reg.GetHigh(), rl_src.reg.GetLow(), shift_amount - 32);
1578 OpRegRegImm(kOpLsl, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount);
1580 EncodeShift(kArmLsr, 32 - shift_amount));
1581 OpRegRegImm(kOpLsl, rl_result.reg.GetLow(), rl_src.reg.GetLow(), shift_amount);
1586 if (shift_amount
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/art/compiler/optimizing/
H A Dcommon_arm64.h176 return vixl::Operand(mem_op.regoffset(), mem_op.extend(), mem_op.shift_amount());
178 return vixl::Operand(mem_op.regoffset(), mem_op.shift(), mem_op.shift_amount());
/art/compiler/dex/quick/x86/
H A Dint_x86.cc662 int shift_amount = CTZ(imm); local
663 OpRegImm(kOpAsr, rl_result.reg, shift_amount);
1755 int shift_amount = CTZ(val); local
1759 shift_amount, flags);
2198 int shift_amount = CTZ(imm); local
2199 OpRegImm(kOpAsr, rl_result.reg, shift_amount);
2552 RegLocation rl_src, int shift_amount, int flags) {
2573 OpRegRegImm(op, rl_result.reg, rl_src.reg, shift_amount);
2578 DCHECK_NE(shift_amount, 1); // Prevent a double store from happening.
2579 if (shift_amount
2551 GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, int shift_amount, int flags) argument
2640 int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; local
[all...]
H A Dcodegen_x86.h780 * @param shift_amount How much to shift.
785 RegLocation rl_src, int shift_amount, int flags);
/art/compiler/dex/quick/mips/
H A Dint_mips.cc868 int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; local
870 if (shift_amount == 0) {
892 OpRegRegImm(op, rl_result.reg, rl_src1.reg, shift_amount);
/art/compiler/dex/quick/arm64/
H A Dint_arm64.cc1347 int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; local
1349 if (shift_amount == 0) {
1371 OpRegRegImm(op, rl_result.reg, rl_src.reg, shift_amount);

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