Searched refs:spill (Results 1 - 12 of 12) sorted by relevance
| /art/compiler/utils/ |
| H A D | managed_register.h | 119 ManagedRegisterSpill spill(__x);
120 std::vector<ManagedRegisterSpill>::push_back(spill);
124 ManagedRegisterSpill spill(__x, __size);
125 std::vector<ManagedRegisterSpill>::push_back(spill);
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| /art/runtime/arch/arm/ |
| H A D | jni_entrypoints_arm.S | 24 push {r0, r1, r2, r3, lr} @ spill regs
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| H A D | quick_entrypoints_arm.S | 387 push {r4, r5, r6, r7, r8, r9, r10, r11, lr} @ spill regs
439 pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} @ restore spill regs
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| /art/compiler/jni/quick/x86/ |
| H A D | calling_convention_x86.cc | 126 // We spill the argument registers on X86 to free them up for scratch use, we then assume
136 ManagedRegisterSpill spill(in_reg, size, spill_offset);
137 entry_spills_.push_back(spill);
142 // We have to spill the second half of the long.
187 // Plus return value spill area size
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| /art/compiler/jni/quick/x86_64/ |
| H A D | calling_convention_x86_64.cc | 106 // We spill the argument registers on X86 to free them up for scratch use, we then assume
115 ManagedRegisterSpill spill(in_reg, size, spill_offset);
116 entry_spills_.push_back(spill);
156 // Plus return value spill area size
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| /art/compiler/utils/x86_64/ |
| H A D | assembler_x86_64.cc | 2365 x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); local
2366 if (spill.IsCpuRegister()) {
2367 pushq(spill.AsCpuRegister());
2370 cfi_.RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0);
2380 // spill xmms
2383 x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); local
2384 if (spill.IsXmmRegister()) {
2386 movsd(Address(CpuRegister(RSP), offset), spill.AsXmmRegister());
2387 cfi_.RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset);
2396 ManagedRegisterSpill spill local
2424 x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); local
2437 x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); local
[all...] |
| H A D | assembler_x86_64_test.cc | 1100 // TODO: more interesting spill registers / entry spills.
1102 // Two random spill regs.
1109 ManagedRegisterSpill spill(ManagedFromCpu(x86_64::RAX), 8, 0);
1110 entry_spills.push_back(spill);
1145 // TODO: more interesting spill registers / entry spills.
1147 // Two random spill regs.
1160 // 2) Pop spill regs.
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| /art/compiler/utils/x86/ |
| H A D | assembler_x86.cc | 1719 Register spill = spill_regs.at(i).AsX86().AsCpuRegister(); local
1720 pushl(spill);
1723 cfi_.RelOffset(DWARFReg(spill), 0);
1737 ManagedRegisterSpill spill = entry_spills.at(i); local
1738 if (spill.AsX86().IsCpuRegister()) {
1739 int offset = frame_size + spill.getSpillOffset();
1740 movl(Address(ESP, offset), spill.AsX86().AsCpuRegister());
1742 DCHECK(spill.AsX86().IsXmmRegister());
1743 if (spill.getSize() == 8) {
1744 movsd(Address(ESP, frame_size + spill
1761 Register spill = spill_regs.at(i).AsX86().AsCpuRegister(); local
[all...] |
| /art/compiler/utils/arm/ |
| H A D | assembler_arm.cc | 423 ManagedRegisterSpill spill = entry_spills.at(i);
424 offset += spill.getSize();
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| /art/compiler/utils/arm64/ |
| H A D | assembler_arm64.cc | 734 ManagedRegisterSpill spill = entry_spills.at(i); local
735 offset += spill.getSize();
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 1097 ManagedRegisterSpill spill = entry_spills.at(i); local
1098 int32_t size = spill.getSize();
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| /art/runtime/arch/mips/ |
| H A D | quick_entrypoints_mips.S | 503 addiu $sp, $sp, -16 # spill s0, s1, fp, ra
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