Searched refs:sreg (Results 1 - 12 of 12) sorted by relevance

/art/compiler/dex/
H A Dtype_inference_test.cc460 void MapVRegToSReg(int vreg, int32_t sreg, const BasicBlockId (&bb_ids)[count]) { argument
467 bb->data_flow_info->vreg_to_ssa_map_exit[vreg] = sreg;
1032 for (int32_t sreg = 0; sreg != arraysize(expectations); ++sreg) {
1033 ExpectSRegType(sreg, expectations[sreg]);
1058 for (int32_t sreg = 0; sreg != arraysize(expectations); ++sreg) {
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H A Dmir_graph.h189 * In general, vreg/sreg describe Dalvik registers that originated with dx. However,
858 uint32_t GetUseCount(int sreg) const {
859 DCHECK_LT(static_cast<size_t>(sreg), use_counts_.size());
860 return use_counts_[sreg];
863 uint32_t GetRawUseCount(int sreg) const {
864 DCHECK_LT(static_cast<size_t>(sreg), raw_use_counts_.size());
865 return raw_use_counts_[sreg];
1001 * the sreg provided by the temp will be invalidated on next ssa recalculation.
H A Dlocal_value_numbering_test.cc187 for (int32_t sreg : sregs) {
188 cu_.mir_graph->reg_location_[sreg].wide = true;
189 cu_.mir_graph->reg_location_[sreg + 1].wide = true;
190 cu_.mir_graph->reg_location_[sreg + 1].high_word = true;
567 DEF_APUT(Instruction::APUT, 2u, 20u, 41u), // May alias with index for sreg 40u.
H A Dlocal_value_numbering.cc375 // RETURN or PHI+RETURN. We need only sreg value maps.
947 // RETURN or PHI+RETURN. We need only sreg value maps.
1137 uint16_t sreg = *uses; local
1140 auto local_it = mir_lvn->sreg_value_map_.find(sreg);
1144 uint16_t value_name = gvn_->FindValue(kNoValue, sreg, kNoValue, kNoValue);
H A Dglobal_value_numbering_test.cc295 for (int32_t sreg : sregs) {
296 cu_.mir_graph->reg_location_[sreg].wide = true;
297 cu_.mir_graph->reg_location_[sreg + 1].wide = true;
298 cu_.mir_graph->reg_location_[sreg + 1].high_word = true;
1391 // For the IGET that loads sreg 3u using base 2u, the following IPUT creates a dependency
H A Dgvn_dead_code_elimination_test.cc413 for (int32_t sreg : sregs) {
414 cu_.mir_graph->reg_location_[sreg].wide = true;
415 cu_.mir_graph->reg_location_[sreg + 1].wide = true;
416 cu_.mir_graph->reg_location_[sreg + 1].high_word = true;
/art/compiler/utils/
H A Dassembler_test.h190 std::ostringstream sreg; local
191 sreg << imm;
192 std::string imm_string = sreg.str();
442 std::ostringstream sreg; local
443 sreg << imm;
444 std::string imm_string = sreg.str();
462 std::ostringstream sreg; local
465 sreg << reg;
469 sreg << GetSecondaryRegisterName(reg);
473 sreg << GetTertiaryRegisterNam
484 std::ostringstream sreg; local
529 std::ostringstream sreg; local
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/art/compiler/utils/arm/
H A Dassembler_arm_test.h105 std::ostringstream sreg; local
106 sreg << i;
107 std::string imm_string = sreg.str();
116 std::ostringstream sreg; local
117 sreg << j;
118 std::string imm_string = sreg.str();
198 std::ostringstream sreg; local
199 sreg << i;
200 std::string imm_string = sreg.str();
208 std::ostringstream sreg; local
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/art/compiler/utils/arm64/
H A Dmanaged_register_arm64_test.cc169 Arm64ManagedRegister sreg = Arm64ManagedRegister::FromSRegister(S0); local
175 EXPECT_TRUE(reg.Overlaps(sreg));
181 sreg = Arm64ManagedRegister::FromSRegister(S1);
187 EXPECT_TRUE(reg.Overlaps(sreg));
193 sreg = Arm64ManagedRegister::FromSRegister(S20);
199 EXPECT_TRUE(reg.Overlaps(sreg));
205 sreg = Arm64ManagedRegister::FromSRegister(S31);
211 EXPECT_TRUE(reg.Overlaps(sreg));
/art/compiler/dex/quick/
H A Dcodegen_util.cc1374 int32_t sreg = first_vreg_to_ssa_map[vreg]; local
1375 if (sreg != INVALID_SREG && mir_graph_->reg_location_[sreg].ref &&
1376 !mir_graph_->IsConstantNullRef(mir_graph_->reg_location_[sreg])) {
/art/compiler/dex/quick/x86/
H A Dcodegen_x86.h797 * @param sreg Symbolic register.
801 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val);
H A Dint_x86.cc1637 void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { argument
1638 UNUSED(sreg);

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