/external/zlib/src/contrib/iostream3/ |
H A D | zfstream.h | 425 T2 v2); member in class:gzomanip2 451 T2 v2) 452 : func(f), val1(v1), val2(v2)
|
/external/webp/src/enc/ |
H A D | quant.c | 839 const int v2 = abs(DCs[5]); local 841 max_v = (v2 > max_v) ? v2 : max_v;
|
/external/webrtc/src/common_audio/signal_processing/include/ |
H A D | signal_processing_library.h | 169 #define WEBRTC_SPL_MEMCPY_W8(v1, v2, length) \ 170 memcpy(v1, v2, (length) * sizeof(char)) 171 #define WEBRTC_SPL_MEMCPY_W16(v1, v2, length) \ 172 memcpy(v1, v2, (length) * sizeof(WebRtc_Word16)) 174 #define WEBRTC_SPL_MEMMOVE_W16(v1, v2, length) \ 175 memmove(v1, v2, (length) * sizeof(WebRtc_Word16))
|
/external/webrtc/src/system_wrappers/source/ |
H A D | data_log_helpers_unittest.cc | 22 webrtc::ValueContainer<int> v2(c); 25 v2.ToString(&s2); 28 v1 = v2; 37 webrtc::ValueContainer<double> v2(c); 40 v2.ToString(&s2); 43 v1 = v2;
|
/external/vogar/lib/ |
H A D | guava.jar | META-INF/ META-INF/MANIFEST.MF com/ com/google/ com/google/common/ com/google/common/annotations/ ... |
H A D | mockito-all-1.8.5.jar | META-INF/ META-INF/MANIFEST.MF org/ org/hamcrest/ org/hamcrest/core/ org/hamcrest/internal/ org/ ... |
/external/vixl/examples/ |
H A D | neon-matrix-multiply.cc | 41 // v<v_out> corresponds to a column of the output matrix (v0, v1, v2 or v3). 81 __ Movi(v2.V16B(), 0); 89 // Store the resulting matrix from v0, v1, v2 and v3. 90 __ St1(v0.V4S(), v1.V4S(), v2.V4S(), v3.V4S(), MemOperand(x0));
|
/external/vixl/test/ |
H A D | test-assembler-a64.cc | 2916 __ Ld1(v2.V8B(), MemOperand(x17)); 2972 __ Ld1(v2.V8B(), MemOperand(x17, x23, PostIndex)); 3025 __ Ld1(v2.V16B(), MemOperand(x17)); 3073 __ Ld1(v2.V16B(), MemOperand(x17, x22, PostIndex)); 3134 __ Ld1(v2.S(), i, MemOperand(x17)); 3182 __ Ld2(v2.V8B(), v3.V8B(), MemOperand(x17)); 3221 __ Ld2(v2.V8B(), v3.V8B(), MemOperand(x17, x22, PostIndex)); 3261 __ Ld2(v2.V16B(), v3.V16B(), MemOperand(x17)); 3305 __ Ld2(v2.V16B(), v3.V16B(), MemOperand(x17, x22, PostIndex)); 3357 __ Ld2(v2 [all...] |
H A D | test-disasm-a64.cc | 2845 COMPARE(Ld1(v1.M, v2.M, MemOperand(x16)), \ 2846 "ld1 {v1." S ", v2." S "}, [x16]"); \ 2853 COMPARE(Ld2(v1.M, v2.M, MemOperand(x16)), \ 2854 "ld2 {v1." S ", v2." S "}, [x16]"); \ 2867 COMPARE(Ld1(v1.M, v2.M, MemOperand(x16, x21, PostIndex)), \ 2868 "ld1 {v1." S ", v2." S "}, [x16], x21"); \ 2875 COMPARE(Ld2(v1.M, v2.M, MemOperand(x16, x21, PostIndex)), \ 2876 "ld2 {v1." S ", v2." S "}, [x16], x21"); \ 2890 COMPARE(Ld1(v2.V4H(), v3.V4H(), MemOperand(x17, 16, PostIndex)), 2891 "ld1 {v2 [all...] |
H A D | test-simulator-a64.cc | 1612 VRegister vm = v2.V16B(); 1838 VRegister vm = v2.V16B();
|
/external/valgrind/memcheck/tests/vbit-test/ |
H A D | binary.c | 8 /* A convenience function to compute either v1 & ~v2 & val2 or 9 v1 & ~v2 & ~val2 depending on INVERT_VAL2. */ 11 and_combine(vbits_t v1, vbits_t v2, value_t val2, int invert_val2) argument 13 assert(v1.num_bits == v2.num_bits); 15 vbits_t new = { .num_bits = v2.num_bits }; 18 switch (v2.num_bits) { 28 switch (v2.num_bits) { 30 new.bits.u8 = (v1.bits.u8 & ~v2.bits.u8 & val2.u8) & 0xff; 33 new.bits.u16 = (v1.bits.u16 & ~v2.bits.u16 & val2.u16) & 0xffff; 36 new.bits.u32 = (v1.bits.u32 & ~v2 [all...] |
H A D | vbits.c | 129 equal_vbits(vbits_t v1, vbits_t v2) argument 131 assert(v1.num_bits == v2.num_bits); 134 case 1: return v1.bits.u32 == v2.bits.u32; 135 case 8: return v1.bits.u8 == v2.bits.u8; 136 case 16: return v1.bits.u16 == v2.bits.u16; 137 case 32: return v1.bits.u32 == v2.bits.u32; 138 case 64: return v1.bits.u64 == v2.bits.u64; 139 case 128: return v1.bits.u128[0] == v2.bits.u128[0] && 140 v1.bits.u128[1] == v2.bits.u128[1]; 141 case 256: return v1.bits.u256[0] == v2 348 or_vbits(vbits_t v1, vbits_t v2) argument 376 and_vbits(vbits_t v1, vbits_t v2) argument 404 concat_vbits(vbits_t v1, vbits_t v2) argument [all...] |
/external/valgrind/memcheck/tests/ |
H A D | wrap6.c | 23 register UInt v2 = vec[2-1]; \ 53 v2 = ROL(v2,2); \ 82 sum ^= (v1-v2); \
|
/external/valgrind/none/tests/amd64/ |
H A D | amd64locked.c | 224 Long o, s, z, a, c, p, v1, v2, flags_in; \ 228 for (v2 = 0; v2 < NVALS; v2++) { \ 245 e_val = val[v2]; \ 319 Long o, s, z, a, c, p, v2, flags_in; \ 322 for (v2 = 0; v2 < NVALS; v2++) { \ 338 e_val = val[v2]; \ [all...] |
/external/valgrind/none/tests/arm64/ |
H A D | fp_and_simd.stdout.exp | 33 faddp v2.2d, v23.2d, v11.2d 200d17261638b12a2a6a07863ec28077 31005fb9ada2074bf63a63fedcb4d29c 3f871736dc9ac5357446eb65e4e703bb 7446eb65e4e703bbf63a63fedcb4d29c 31005fb9ada2074bf63a63fedcb4d29c 3f871736dc9ac5357446eb65e4e703bb fpsr=00000000 34 faddp v2.4s, v23.4s, v11.4s 139832afee423c3d6930e0fad3ba39c4 4969e55289753f038f7980d1535979e5 80c745ef729f1792ccd7e987538166e1 729f1792538163814969e552535979e5 4969e55289753f038f7980d1535979e5 80c745ef729f1792ccd7e987538166e1 fpsr=00000000 35 faddp v2.2s, v23.2s, v11.2s 237d5fcd3f71f6e8e6230d4d4add00ad e309aef8a605af130821eb96e737777e b5a9377eb31749ef710cf757885d2728 0000000000000000710cf757e737777e e309aef8a605af130821eb96e737777e b5a9377eb31749ef710cf757885d2728 fpsr=00000000 14348 fcmeq v2.2d, v23.2d, v11.2d cc1edb8be1f468b449e87dd22eef6c52 978034cf287f804e7ece8cedd52fd9f0 fce269d39a5e0499955acef5dc851526 00000000000000000000000000000000 978034cf287f804e7ece8cedd52fd9f0 fce269d39a5e0499955acef5dc851526 fpsr=00000000 14349 fcmeq v2.4s, v23.4s, v11.4s 5fb571c4030f1099df95b2efece91f25 e736af3548e98874b77061b100f6f0e4 ea7c8164898e962c3416dcbd26ef99c8 00000000000000000000000000000000 e736af3548e98874b77061b100f6f0e4 ea7c8164898e962c3416dcbd26ef99c8 fpsr=00000000 14350 fcmeq v2.2s, v23.2s, v11.2s 8c933ae059e561a39b2b9f689a30b104 d692722d428ef08c5d9844bf02c9dbf3 fc9b79b479f5beff0576cf3daca36814 00000000000000000000000000000000 d692722d428ef08c5d9844bf02c9dbf3 fc9b79b479f5beff0576cf3daca36814 fpsr=00000000 14351 fcmge v2.2d, v23.2d, v11.2d f66d3a7346ec2123a1ddc8521db966c3 094784497ae17de8947bba2bbe9be0f0 d8f15457cc0940642cb02a895394c6db ffffffffffffffff0000000000000000 094784497ae17de8947bba2bbe9be0f0 d8f15457cc0940642cb02a895394c6db fpsr=00000000 14352 fcmge v2.4s, v23.4s, v11.4s 42f777113096137016e0b3bf59768237 230be71e5456f1df7e4d47091a6043af 223317e0e73ee0b2cef672b500b6f7f4 ffffffffffffffffffffffffffffffff 230be71e5456f1df7e4d47091a6043af 223317e0e73ee0b2cef672b500b6f7f4 fpsr=00000000 14353 fcmge v2.2s, v23.2s, v11.2s 13e5f24e7959fbdb1d68e1c4325d4934 c890a041336112c341426e6df80d4606 7c14c5e52d06623b0d7c2ad595fd3f30 0000000000000000ffffffff00000000 c890a041336112c341426e6df80d4606 7c14c5e52d06623b0d7c2ad595fd3f30 fpsr=00000000 14354 fcmgt v2 [all...] |
/external/valgrind/none/tests/s390x/ |
H A D | add.h | 53 unsigned long tmp = s1, v2; \ 64 v2 = (((signed long)((unsigned long)0x##s2 << 56)) >> 56); \ 65 printf(#insn " " #CARRY " + %16.16lX + %16.16lX = %16.16lX (cc=%d)\n", s1, v2, tmp, cc); \
|
H A D | bfp-3.c | 6 void maebr(float v1, float v2, float v3) argument 11 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3)); 12 printf("maebr %f * %f + %f -> %f\n", v2, v3, v1, r1); 15 void madbr(double v1, double v2, double v3) argument 20 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3)); 21 printf("madbr %f * %f + %f -> %f\n", v2, v3, v1, r1); 24 void msebr(float v1, float v2, float v3) argument 29 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3)); 30 printf("msebr %f * %f - %f -> %f\n", v2, v3, v1, r1); 33 void msdbr(double v1, double v2, doubl argument [all...] |
H A D | bfp-4.c | 5 void cebr(float v1, float v2) argument 12 : [psw]"=d"(cc) : [r1]"f"(v1), [r2]"f"(v2) : "cc"); 14 printf("cfebr: %f == %f\n", v1, v2); 16 printf("cfebr: %f < %f\n", v1, v2); 18 printf("cfebr: %f > %f\n", v1, v2); 21 void cdbr(double v1, double v2) argument 28 : [psw]"=d"(cc) : [r1]"f"(v1), [r2]"f"(v2) : "cc"); 30 printf("cdebr: %f == %f\n", v1, v2); 32 printf("cdebr: %f < %f\n", v1, v2); 34 printf("cdebr: %f > %f\n", v1, v2); [all...] |
H A D | comp-1.c | 21 #define SCOMP_REG_REG(insn, v1, v2) \ 25 int64_t op2 = v2; \ 38 #define SCOMP_REG_MEM(insn, v1, v2, op2_t) \ 42 op2_t op2 = v2; \ 55 #define SCOMP_REG_IMM(insn, v1, v2) \ 59 asm volatile( insn(8, v2) \ 66 #insn, op1, (int64_t)v2, cc); \
|
H A D | comp-2.c | 21 #define SCOMP_REG_REG(insn, v1, v2) \ 25 uint64_t op2 = v2; \ 38 #define SCOMP_REG_MEM(insn, v1, v2, op2_t) \ 42 op2_t op2 = v2; \ 55 #define SCOMP_REG_IMM(insn, v1, v2) \ 59 asm volatile( insn(8, v2) \ 66 #insn, op1, (uint64_t)v2, cc); \
|
H A D | dfp-3.c | 27 #define COMPARE(insn, v1, v2, type) \ 30 CMP_DFP(insn, v1, v2, type, cc); \ 46 DFP_VAL_PRINT(v2, type); \
|
H A D | spechelper-algr.c | 24 unsigned long v1, v2; local 29 v1 = v2 = 0; 31 if (branch(0, v1, v2)) ++wrong; else ++ok; 32 if (branch(1, v1, v2)) ++wrong; else ++ok; 33 if (branch(2, v1, v2)) ++wrong; else ++ok; 34 if (branch(3, v1, v2)) ++wrong; else ++ok; 35 if (branch(4, v1, v2)) ++wrong; else ++ok; 36 if (branch(5, v1, v2)) ++wrong; else ++ok; 37 if (branch(6, v1, v2)) ++wrong; else ++ok; 38 if (branch(7, v1, v2)) 57 unsigned long v1, v2; local 91 unsigned long v1, v2; local 127 unsigned long v1, v2; local [all...] |
H A D | spechelper-alr.c | 24 unsigned v1, v2; local 29 v1 = v2 = 0; 31 if (branch(0, v1, v2)) ++wrong; else ++ok; 32 if (branch(1, v1, v2)) ++wrong; else ++ok; 33 if (branch(2, v1, v2)) ++wrong; else ++ok; 34 if (branch(3, v1, v2)) ++wrong; else ++ok; 35 if (branch(4, v1, v2)) ++wrong; else ++ok; 36 if (branch(5, v1, v2)) ++wrong; else ++ok; 37 if (branch(6, v1, v2)) ++wrong; else ++ok; 38 if (branch(7, v1, v2)) 57 unsigned v1, v2; local 91 unsigned v1, v2; local 127 unsigned v1, v2; local [all...] |
H A D | spechelper-clr.c | 22 int wrong, ok, v1, v2; local 26 v1 = v2 = 42; 29 if (branch(0, v1, v2)) ++wrong; else ++ok; 30 if (branch(1, v1, v2)) ++wrong; else ++ok; 31 if (branch(2, v1, v2)) ++wrong; else ++ok; 32 if (branch(3, v1, v2)) ++wrong; else ++ok; 33 if (branch(4, v1, v2)) ++wrong; else ++ok; 34 if (branch(5, v1, v2)) ++wrong; else ++ok; 35 if (branch(6, v1, v2)) ++wrong; else ++ok; 36 if (branch(7, v1, v2)) 55 int wrong, ok, v1, v2; local 88 int wrong, ok, v1, v2; local [all...] |
H A D | spechelper-cr.c | 22 int wrong, ok, v1, v2; local 26 v1 = v2 = 42; 29 if (branch(0, v1, v2)) ++wrong; else ++ok; 30 if (branch(1, v1, v2)) ++wrong; else ++ok; 31 if (branch(2, v1, v2)) ++wrong; else ++ok; 32 if (branch(3, v1, v2)) ++wrong; else ++ok; 33 if (branch(4, v1, v2)) ++wrong; else ++ok; 34 if (branch(5, v1, v2)) ++wrong; else ++ok; 35 if (branch(6, v1, v2)) ++wrong; else ++ok; 36 if (branch(7, v1, v2)) 55 int wrong, ok, v1, v2; local 88 int wrong, ok, v1, v2; local [all...] |