Searched refs:X0100 (Results 1 - 1 of 1) sorted by relevance
| /external/valgrind/VEX/priv/ |
| H A D | host_arm_defs.c | 2717 #define X0100 BITS4(0,1,0,0) macro
2977 case ARMalu_ADD: subopc = X0100; break;
3544 case ARMvfp_MUL: pqrs = X0100; break;
3569 case ARMvfp_MUL: pqrs = X0100; break;
3590 insn = XXXXXXXX(0xE, X1110,X1011,X0000,dD,X1011,X0100,dM);
3596 insn = XXXXXXXX(0xE, X1110,X1011,X0001,dD,X1011,X0100,dM);
3641 UInt insn = XXXXXXXX(0xE, X1110, X1011, X0100, dD, X1011, X0100, dM);
3651 UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM);
3745 X1011, X0100, reg
4861 #undef X0100 macro
[all...] |
Completed in 25 milliseconds