int_arm.cc revision 8dea81ca9c0201ceaa88086b927a5838a06a3e69
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains codegen for the Thumb2 ISA. */ 18 19#include "arm_lir.h" 20#include "codegen_arm.h" 21#include "dex/quick/mir_to_lir-inl.h" 22#include "entrypoints/quick/quick_entrypoints.h" 23#include "mirror/array.h" 24 25namespace art { 26 27LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { 28 OpRegReg(kOpCmp, src1, src2); 29 return OpCondBranch(cond, target); 30} 31 32/* 33 * Generate a Thumb2 IT instruction, which can nullify up to 34 * four subsequent instructions based on a condition and its 35 * inverse. The condition applies to the first instruction, which 36 * is executed if the condition is met. The string "guide" consists 37 * of 0 to 3 chars, and applies to the 2nd through 4th instruction. 38 * A "T" means the instruction is executed if the condition is 39 * met, and an "E" means the instruction is executed if the condition 40 * is not met. 41 */ 42LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) { 43 int mask; 44 int mask3 = 0; 45 int mask2 = 0; 46 int mask1 = 0; 47 ArmConditionCode code = ArmConditionEncoding(ccode); 48 int cond_bit = code & 1; 49 int alt_bit = cond_bit ^ 1; 50 51 // Note: case fallthroughs intentional 52 switch (strlen(guide)) { 53 case 3: 54 mask1 = (guide[2] == 'T') ? cond_bit : alt_bit; 55 case 2: 56 mask2 = (guide[1] == 'T') ? cond_bit : alt_bit; 57 case 1: 58 mask3 = (guide[0] == 'T') ? cond_bit : alt_bit; 59 break; 60 case 0: 61 break; 62 default: 63 LOG(FATAL) << "OAT: bad case in OpIT"; 64 } 65 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | 66 (1 << (3 - strlen(guide))); 67 return NewLIR2(kThumb2It, code, mask); 68} 69 70void ArmMir2Lir::UpdateIT(LIR* it, const char* new_guide) { 71 int mask; 72 int mask3 = 0; 73 int mask2 = 0; 74 int mask1 = 0; 75 ArmConditionCode code = static_cast<ArmConditionCode>(it->operands[0]); 76 int cond_bit = code & 1; 77 int alt_bit = cond_bit ^ 1; 78 79 // Note: case fallthroughs intentional 80 switch (strlen(new_guide)) { 81 case 3: 82 mask1 = (new_guide[2] == 'T') ? cond_bit : alt_bit; 83 case 2: 84 mask2 = (new_guide[1] == 'T') ? cond_bit : alt_bit; 85 case 1: 86 mask3 = (new_guide[0] == 'T') ? cond_bit : alt_bit; 87 break; 88 case 0: 89 break; 90 default: 91 LOG(FATAL) << "OAT: bad case in UpdateIT"; 92 } 93 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | 94 (1 << (3 - strlen(new_guide))); 95 it->operands[1] = mask; 96} 97 98void ArmMir2Lir::OpEndIT(LIR* it) { 99 // TODO: use the 'it' pointer to do some checks with the LIR, for example 100 // we could check that the number of instructions matches the mask 101 // in the IT instruction. 102 CHECK(it != nullptr); 103 GenBarrier(); 104} 105 106/* 107 * 64-bit 3way compare function. 108 * mov rX, #-1 109 * cmp op1hi, op2hi 110 * blt done 111 * bgt flip 112 * sub rX, op1lo, op2lo (treat as unsigned) 113 * beq done 114 * ite hi 115 * mov(hi) rX, #-1 116 * mov(!hi) rX, #1 117 * flip: 118 * neg rX 119 * done: 120 */ 121void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 122 LIR* target1; 123 LIR* target2; 124 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 125 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 126 RegStorage t_reg = AllocTemp(); 127 LoadConstant(t_reg, -1); 128 OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 129 LIR* branch1 = OpCondBranch(kCondLt, NULL); 130 LIR* branch2 = OpCondBranch(kCondGt, NULL); 131 OpRegRegReg(kOpSub, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 132 LIR* branch3 = OpCondBranch(kCondEq, NULL); 133 134 LIR* it = OpIT(kCondHi, "E"); 135 NewLIR2(kThumb2MovI8M, t_reg.GetReg(), ModifiedImmediate(-1)); 136 LoadConstant(t_reg, 1); 137 OpEndIT(it); 138 139 target2 = NewLIR0(kPseudoTargetLabel); 140 OpRegReg(kOpNeg, t_reg, t_reg); 141 142 target1 = NewLIR0(kPseudoTargetLabel); 143 144 RegLocation rl_temp = LocCReturn(); // Just using as template, will change 145 rl_temp.reg.SetReg(t_reg.GetReg()); 146 StoreValue(rl_dest, rl_temp); 147 FreeTemp(t_reg); 148 149 branch1->target = target1; 150 branch2->target = target2; 151 branch3->target = branch1->target; 152} 153 154void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 155 int64_t val, ConditionCode ccode) { 156 int32_t val_lo = Low32Bits(val); 157 int32_t val_hi = High32Bits(val); 158 DCHECK_GE(ModifiedImmediate(val_lo), 0); 159 DCHECK_GE(ModifiedImmediate(val_hi), 0); 160 LIR* taken = &block_label_list_[bb->taken]; 161 LIR* not_taken = &block_label_list_[bb->fall_through]; 162 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 163 RegStorage low_reg = rl_src1.reg.GetLow(); 164 RegStorage high_reg = rl_src1.reg.GetHigh(); 165 166 if (val == 0 && (ccode == kCondEq || ccode == kCondNe)) { 167 RegStorage t_reg = AllocTemp(); 168 NewLIR4(kThumb2OrrRRRs, t_reg.GetReg(), low_reg.GetReg(), high_reg.GetReg(), 0); 169 FreeTemp(t_reg); 170 OpCondBranch(ccode, taken); 171 return; 172 } 173 174 switch (ccode) { 175 case kCondEq: 176 case kCondNe: 177 OpCmpImmBranch(kCondNe, high_reg, val_hi, (ccode == kCondEq) ? not_taken : taken); 178 break; 179 case kCondLt: 180 OpCmpImmBranch(kCondLt, high_reg, val_hi, taken); 181 OpCmpImmBranch(kCondGt, high_reg, val_hi, not_taken); 182 ccode = kCondUlt; 183 break; 184 case kCondLe: 185 OpCmpImmBranch(kCondLt, high_reg, val_hi, taken); 186 OpCmpImmBranch(kCondGt, high_reg, val_hi, not_taken); 187 ccode = kCondLs; 188 break; 189 case kCondGt: 190 OpCmpImmBranch(kCondGt, high_reg, val_hi, taken); 191 OpCmpImmBranch(kCondLt, high_reg, val_hi, not_taken); 192 ccode = kCondHi; 193 break; 194 case kCondGe: 195 OpCmpImmBranch(kCondGt, high_reg, val_hi, taken); 196 OpCmpImmBranch(kCondLt, high_reg, val_hi, not_taken); 197 ccode = kCondUge; 198 break; 199 default: 200 LOG(FATAL) << "Unexpected ccode: " << ccode; 201 } 202 OpCmpImmBranch(ccode, low_reg, val_lo, taken); 203} 204 205void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { 206 RegLocation rl_result; 207 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); 208 RegLocation rl_dest = mir_graph_->GetDest(mir); 209 // Avoid using float regs here. 210 RegisterClass src_reg_class = rl_src.ref ? kRefReg : kCoreReg; 211 RegisterClass result_reg_class = rl_dest.ref ? kRefReg : kCoreReg; 212 rl_src = LoadValue(rl_src, src_reg_class); 213 ConditionCode ccode = mir->meta.ccode; 214 if (mir->ssa_rep->num_uses == 1) { 215 // CONST case 216 int true_val = mir->dalvikInsn.vB; 217 int false_val = mir->dalvikInsn.vC; 218 rl_result = EvalLoc(rl_dest, result_reg_class, true); 219 // Change kCondNe to kCondEq for the special cases below. 220 if (ccode == kCondNe) { 221 ccode = kCondEq; 222 std::swap(true_val, false_val); 223 } 224 bool cheap_false_val = InexpensiveConstantInt(false_val); 225 if (cheap_false_val && ccode == kCondEq && (true_val == 0 || true_val == -1)) { 226 OpRegRegImm(kOpSub, rl_result.reg, rl_src.reg, -true_val); 227 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 228 LIR* it = OpIT(true_val == 0 ? kCondNe : kCondUge, ""); 229 LoadConstant(rl_result.reg, false_val); 230 OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact 231 } else if (cheap_false_val && ccode == kCondEq && true_val == 1) { 232 OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, 1); 233 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 234 LIR* it = OpIT(kCondLs, ""); 235 LoadConstant(rl_result.reg, false_val); 236 OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact 237 } else if (cheap_false_val && InexpensiveConstantInt(true_val)) { 238 OpRegImm(kOpCmp, rl_src.reg, 0); 239 LIR* it = OpIT(ccode, "E"); 240 LoadConstant(rl_result.reg, true_val); 241 LoadConstant(rl_result.reg, false_val); 242 OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact 243 } else { 244 // Unlikely case - could be tuned. 245 RegStorage t_reg1 = AllocTypedTemp(false, result_reg_class); 246 RegStorage t_reg2 = AllocTypedTemp(false, result_reg_class); 247 LoadConstant(t_reg1, true_val); 248 LoadConstant(t_reg2, false_val); 249 OpRegImm(kOpCmp, rl_src.reg, 0); 250 LIR* it = OpIT(ccode, "E"); 251 OpRegCopy(rl_result.reg, t_reg1); 252 OpRegCopy(rl_result.reg, t_reg2); 253 OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact 254 } 255 } else { 256 // MOVE case 257 RegLocation rl_true = mir_graph_->reg_location_[mir->ssa_rep->uses[1]]; 258 RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]]; 259 rl_true = LoadValue(rl_true, result_reg_class); 260 rl_false = LoadValue(rl_false, result_reg_class); 261 rl_result = EvalLoc(rl_dest, result_reg_class, true); 262 OpRegImm(kOpCmp, rl_src.reg, 0); 263 LIR* it = nullptr; 264 if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { // Is the "true" case already in place? 265 it = OpIT(NegateComparison(ccode), ""); 266 OpRegCopy(rl_result.reg, rl_false.reg); 267 } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { // False case in place? 268 it = OpIT(ccode, ""); 269 OpRegCopy(rl_result.reg, rl_true.reg); 270 } else { // Normal - select between the two. 271 it = OpIT(ccode, "E"); 272 OpRegCopy(rl_result.reg, rl_true.reg); 273 OpRegCopy(rl_result.reg, rl_false.reg); 274 } 275 OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact 276 } 277 StoreValue(rl_dest, rl_result); 278} 279 280void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { 281 RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); 282 RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); 283 // Normalize such that if either operand is constant, src2 will be constant. 284 ConditionCode ccode = mir->meta.ccode; 285 if (rl_src1.is_const) { 286 std::swap(rl_src1, rl_src2); 287 ccode = FlipComparisonOrder(ccode); 288 } 289 if (rl_src2.is_const) { 290 rl_src2 = UpdateLocWide(rl_src2); 291 // Do special compare/branch against simple const operand if not already in registers. 292 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 293 if ((rl_src2.location != kLocPhysReg) && 294 ((ModifiedImmediate(Low32Bits(val)) >= 0) && (ModifiedImmediate(High32Bits(val)) >= 0))) { 295 GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); 296 return; 297 } 298 } 299 LIR* taken = &block_label_list_[bb->taken]; 300 LIR* not_taken = &block_label_list_[bb->fall_through]; 301 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 302 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 303 OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 304 switch (ccode) { 305 case kCondEq: 306 OpCondBranch(kCondNe, not_taken); 307 break; 308 case kCondNe: 309 OpCondBranch(kCondNe, taken); 310 break; 311 case kCondLt: 312 OpCondBranch(kCondLt, taken); 313 OpCondBranch(kCondGt, not_taken); 314 ccode = kCondUlt; 315 break; 316 case kCondLe: 317 OpCondBranch(kCondLt, taken); 318 OpCondBranch(kCondGt, not_taken); 319 ccode = kCondLs; 320 break; 321 case kCondGt: 322 OpCondBranch(kCondGt, taken); 323 OpCondBranch(kCondLt, not_taken); 324 ccode = kCondHi; 325 break; 326 case kCondGe: 327 OpCondBranch(kCondGt, taken); 328 OpCondBranch(kCondLt, not_taken); 329 ccode = kCondUge; 330 break; 331 default: 332 LOG(FATAL) << "Unexpected ccode: " << ccode; 333 } 334 OpRegReg(kOpCmp, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 335 OpCondBranch(ccode, taken); 336} 337 338/* 339 * Generate a register comparison to an immediate and branch. Caller 340 * is responsible for setting branch target field. 341 */ 342LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { 343 LIR* branch; 344 ArmConditionCode arm_cond = ArmConditionEncoding(cond); 345 /* 346 * A common use of OpCmpImmBranch is for null checks, and using the Thumb 16-bit 347 * compare-and-branch if zero is ideal if it will reach. However, because null checks 348 * branch forward to a slow path, they will frequently not reach - and thus have to 349 * be converted to a long form during assembly (which will trigger another assembly 350 * pass). Here we estimate the branch distance for checks, and if large directly 351 * generate the long form in an attempt to avoid an extra assembly pass. 352 * TODO: consider interspersing slowpaths in code following unconditional branches. 353 */ 354 bool skip = ((target != NULL) && (target->opcode == kPseudoThrowTarget)); 355 skip &= ((cu_->code_item->insns_size_in_code_units_ - current_dalvik_offset_) > 64); 356 if (!skip && reg.Low8() && (check_value == 0) && 357 ((arm_cond == kArmCondEq) || (arm_cond == kArmCondNe))) { 358 branch = NewLIR2((arm_cond == kArmCondEq) ? kThumb2Cbz : kThumb2Cbnz, 359 reg.GetReg(), 0); 360 } else { 361 OpRegImm(kOpCmp, reg, check_value); 362 branch = NewLIR2(kThumbBCond, 0, arm_cond); 363 } 364 branch->target = target; 365 return branch; 366} 367 368LIR* ArmMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { 369 LIR* res; 370 int opcode; 371 // If src or dest is a pair, we'll be using low reg. 372 if (r_dest.IsPair()) { 373 r_dest = r_dest.GetLow(); 374 } 375 if (r_src.IsPair()) { 376 r_src = r_src.GetLow(); 377 } 378 if (r_dest.IsFloat() || r_src.IsFloat()) 379 return OpFpRegCopy(r_dest, r_src); 380 if (r_dest.Low8() && r_src.Low8()) 381 opcode = kThumbMovRR; 382 else if (!r_dest.Low8() && !r_src.Low8()) 383 opcode = kThumbMovRR_H2H; 384 else if (r_dest.Low8()) 385 opcode = kThumbMovRR_H2L; 386 else 387 opcode = kThumbMovRR_L2H; 388 res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); 389 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 390 res->flags.is_nop = true; 391 } 392 return res; 393} 394 395void ArmMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { 396 if (r_dest != r_src) { 397 LIR* res = OpRegCopyNoInsert(r_dest, r_src); 398 AppendLIR(res); 399 } 400} 401 402void ArmMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { 403 if (r_dest != r_src) { 404 bool dest_fp = r_dest.IsFloat(); 405 bool src_fp = r_src.IsFloat(); 406 DCHECK(r_dest.Is64Bit()); 407 DCHECK(r_src.Is64Bit()); 408 if (dest_fp) { 409 if (src_fp) { 410 OpRegCopy(r_dest, r_src); 411 } else { 412 NewLIR3(kThumb2Fmdrr, r_dest.GetReg(), r_src.GetLowReg(), r_src.GetHighReg()); 413 } 414 } else { 415 if (src_fp) { 416 NewLIR3(kThumb2Fmrrd, r_dest.GetLowReg(), r_dest.GetHighReg(), r_src.GetReg()); 417 } else { 418 // Handle overlap 419 if (r_src.GetHighReg() == r_dest.GetLowReg()) { 420 DCHECK_NE(r_src.GetLowReg(), r_dest.GetHighReg()); 421 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); 422 OpRegCopy(r_dest.GetLow(), r_src.GetLow()); 423 } else { 424 OpRegCopy(r_dest.GetLow(), r_src.GetLow()); 425 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); 426 } 427 } 428 } 429 } 430} 431 432// Table of magic divisors 433struct MagicTable { 434 uint32_t magic; 435 uint32_t shift; 436 DividePattern pattern; 437}; 438 439static const MagicTable magic_table[] = { 440 {0, 0, DivideNone}, // 0 441 {0, 0, DivideNone}, // 1 442 {0, 0, DivideNone}, // 2 443 {0x55555556, 0, Divide3}, // 3 444 {0, 0, DivideNone}, // 4 445 {0x66666667, 1, Divide5}, // 5 446 {0x2AAAAAAB, 0, Divide3}, // 6 447 {0x92492493, 2, Divide7}, // 7 448 {0, 0, DivideNone}, // 8 449 {0x38E38E39, 1, Divide5}, // 9 450 {0x66666667, 2, Divide5}, // 10 451 {0x2E8BA2E9, 1, Divide5}, // 11 452 {0x2AAAAAAB, 1, Divide5}, // 12 453 {0x4EC4EC4F, 2, Divide5}, // 13 454 {0x92492493, 3, Divide7}, // 14 455 {0x88888889, 3, Divide7}, // 15 456}; 457 458// Integer division by constant via reciprocal multiply (Hacker's Delight, 10-4) 459bool ArmMir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 460 RegLocation rl_src, RegLocation rl_dest, int lit) { 461 if ((lit < 0) || (lit >= static_cast<int>(sizeof(magic_table)/sizeof(magic_table[0])))) { 462 return false; 463 } 464 DividePattern pattern = magic_table[lit].pattern; 465 if (pattern == DivideNone) { 466 return false; 467 } 468 469 RegStorage r_magic = AllocTemp(); 470 LoadConstant(r_magic, magic_table[lit].magic); 471 rl_src = LoadValue(rl_src, kCoreReg); 472 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 473 RegStorage r_hi = AllocTemp(); 474 RegStorage r_lo = AllocTemp(); 475 476 // rl_dest and rl_src might overlap. 477 // Reuse r_hi to save the div result for reminder case. 478 RegStorage r_div_result = is_div ? rl_result.reg : r_hi; 479 480 NewLIR4(kThumb2Smull, r_lo.GetReg(), r_hi.GetReg(), r_magic.GetReg(), rl_src.reg.GetReg()); 481 switch (pattern) { 482 case Divide3: 483 OpRegRegRegShift(kOpSub, r_div_result, r_hi, rl_src.reg, EncodeShift(kArmAsr, 31)); 484 break; 485 case Divide5: 486 OpRegRegImm(kOpAsr, r_lo, rl_src.reg, 31); 487 OpRegRegRegShift(kOpRsub, r_div_result, r_lo, r_hi, 488 EncodeShift(kArmAsr, magic_table[lit].shift)); 489 break; 490 case Divide7: 491 OpRegReg(kOpAdd, r_hi, rl_src.reg); 492 OpRegRegImm(kOpAsr, r_lo, rl_src.reg, 31); 493 OpRegRegRegShift(kOpRsub, r_div_result, r_lo, r_hi, 494 EncodeShift(kArmAsr, magic_table[lit].shift)); 495 break; 496 default: 497 LOG(FATAL) << "Unexpected pattern: " << pattern; 498 } 499 500 if (!is_div) { 501 // div_result = src / lit 502 // tmp1 = div_result * lit 503 // dest = src - tmp1 504 RegStorage tmp1 = r_lo; 505 EasyMultiplyOp ops[2]; 506 507 bool canEasyMultiply = GetEasyMultiplyTwoOps(lit, ops); 508 DCHECK_NE(canEasyMultiply, false); 509 510 GenEasyMultiplyTwoOps(tmp1, r_div_result, ops); 511 OpRegRegReg(kOpSub, rl_result.reg, rl_src.reg, tmp1); 512 } 513 514 StoreValue(rl_dest, rl_result); 515 return true; 516} 517 518// Try to convert *lit to 1 RegRegRegShift/RegRegShift form. 519bool ArmMir2Lir::GetEasyMultiplyOp(int lit, ArmMir2Lir::EasyMultiplyOp* op) { 520 if (IsPowerOfTwo(lit)) { 521 op->op = kOpLsl; 522 op->shift = LowestSetBit(lit); 523 return true; 524 } 525 526 if (IsPowerOfTwo(lit - 1)) { 527 op->op = kOpAdd; 528 op->shift = LowestSetBit(lit - 1); 529 return true; 530 } 531 532 if (IsPowerOfTwo(lit + 1)) { 533 op->op = kOpRsub; 534 op->shift = LowestSetBit(lit + 1); 535 return true; 536 } 537 538 op->op = kOpInvalid; 539 op->shift = 0; 540 return false; 541} 542 543// Try to convert *lit to 1~2 RegRegRegShift/RegRegShift forms. 544bool ArmMir2Lir::GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops) { 545 GetEasyMultiplyOp(lit, &ops[0]); 546 if (GetEasyMultiplyOp(lit, &ops[0])) { 547 ops[1].op = kOpInvalid; 548 ops[1].shift = 0; 549 return true; 550 } 551 552 int lit1 = lit; 553 uint32_t shift = LowestSetBit(lit1); 554 if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) { 555 ops[1].op = kOpLsl; 556 ops[1].shift = shift; 557 return true; 558 } 559 560 lit1 = lit - 1; 561 shift = LowestSetBit(lit1); 562 if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) { 563 ops[1].op = kOpAdd; 564 ops[1].shift = shift; 565 return true; 566 } 567 568 lit1 = lit + 1; 569 shift = LowestSetBit(lit1); 570 if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) { 571 ops[1].op = kOpRsub; 572 ops[1].shift = shift; 573 return true; 574 } 575 576 return false; 577} 578 579// Generate instructions to do multiply. 580// Additional temporary register is required, 581// if it need to generate 2 instructions and src/dest overlap. 582void ArmMir2Lir::GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops) { 583 // tmp1 = ( src << shift1) + [ src | -src | 0 ] 584 // dest = (tmp1 << shift2) + [ src | -src | 0 ] 585 586 RegStorage r_tmp1; 587 if (ops[1].op == kOpInvalid) { 588 r_tmp1 = r_dest; 589 } else if (r_dest.GetReg() != r_src.GetReg()) { 590 r_tmp1 = r_dest; 591 } else { 592 r_tmp1 = AllocTemp(); 593 } 594 595 switch (ops[0].op) { 596 case kOpLsl: 597 OpRegRegImm(kOpLsl, r_tmp1, r_src, ops[0].shift); 598 break; 599 case kOpAdd: 600 OpRegRegRegShift(kOpAdd, r_tmp1, r_src, r_src, EncodeShift(kArmLsl, ops[0].shift)); 601 break; 602 case kOpRsub: 603 OpRegRegRegShift(kOpRsub, r_tmp1, r_src, r_src, EncodeShift(kArmLsl, ops[0].shift)); 604 break; 605 default: 606 DCHECK_EQ(ops[0].op, kOpInvalid); 607 break; 608 } 609 610 switch (ops[1].op) { 611 case kOpInvalid: 612 return; 613 case kOpLsl: 614 OpRegRegImm(kOpLsl, r_dest, r_tmp1, ops[1].shift); 615 break; 616 case kOpAdd: 617 OpRegRegRegShift(kOpAdd, r_dest, r_src, r_tmp1, EncodeShift(kArmLsl, ops[1].shift)); 618 break; 619 case kOpRsub: 620 OpRegRegRegShift(kOpRsub, r_dest, r_src, r_tmp1, EncodeShift(kArmLsl, ops[1].shift)); 621 break; 622 default: 623 LOG(FATAL) << "Unexpected opcode passed to GenEasyMultiplyTwoOps"; 624 break; 625 } 626} 627 628bool ArmMir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 629 EasyMultiplyOp ops[2]; 630 631 if (!GetEasyMultiplyTwoOps(lit, ops)) { 632 return false; 633 } 634 635 rl_src = LoadValue(rl_src, kCoreReg); 636 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 637 638 GenEasyMultiplyTwoOps(rl_result.reg, rl_src.reg, ops); 639 StoreValue(rl_dest, rl_result); 640 return true; 641} 642 643RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 644 RegLocation rl_src2, bool is_div, bool check_zero) { 645 LOG(FATAL) << "Unexpected use of GenDivRem for Arm"; 646 return rl_dest; 647} 648 649RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) { 650 LOG(FATAL) << "Unexpected use of GenDivRemLit for Arm"; 651 return rl_dest; 652} 653 654RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) { 655 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 656 657 // Put the literal in a temp. 658 RegStorage lit_temp = AllocTemp(); 659 LoadConstant(lit_temp, lit); 660 // Use the generic case for div/rem with arg2 in a register. 661 // TODO: The literal temp can be freed earlier during a modulus to reduce reg pressure. 662 rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div); 663 FreeTemp(lit_temp); 664 665 return rl_result; 666} 667 668RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, 669 bool is_div) { 670 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 671 if (is_div) { 672 // Simple case, use sdiv instruction. 673 OpRegRegReg(kOpDiv, rl_result.reg, reg1, reg2); 674 } else { 675 // Remainder case, use the following code: 676 // temp = reg1 / reg2 - integer division 677 // temp = temp * reg2 678 // dest = reg1 - temp 679 680 RegStorage temp = AllocTemp(); 681 OpRegRegReg(kOpDiv, temp, reg1, reg2); 682 OpRegReg(kOpMul, temp, reg2); 683 OpRegRegReg(kOpSub, rl_result.reg, reg1, temp); 684 FreeTemp(temp); 685 } 686 687 return rl_result; 688} 689 690bool ArmMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) { 691 DCHECK_EQ(cu_->instruction_set, kThumb2); 692 RegLocation rl_src1 = info->args[0]; 693 RegLocation rl_src2 = info->args[1]; 694 rl_src1 = LoadValue(rl_src1, kCoreReg); 695 rl_src2 = LoadValue(rl_src2, kCoreReg); 696 RegLocation rl_dest = InlineTarget(info); 697 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 698 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); 699 LIR* it = OpIT((is_min) ? kCondGt : kCondLt, "E"); 700 OpRegReg(kOpMov, rl_result.reg, rl_src2.reg); 701 OpRegReg(kOpMov, rl_result.reg, rl_src1.reg); 702 OpEndIT(it); 703 StoreValue(rl_dest, rl_result); 704 return true; 705} 706 707bool ArmMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { 708 RegLocation rl_src_address = info->args[0]; // long address 709 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] 710 RegLocation rl_dest = InlineTarget(info); 711 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 712 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 713 if (size == k64) { 714 // Fake unaligned LDRD by two unaligned LDR instructions on ARMv7 with SCTLR.A set to 0. 715 if (rl_address.reg.GetReg() != rl_result.reg.GetLowReg()) { 716 Load32Disp(rl_address.reg, 0, rl_result.reg.GetLow()); 717 Load32Disp(rl_address.reg, 4, rl_result.reg.GetHigh()); 718 } else { 719 Load32Disp(rl_address.reg, 4, rl_result.reg.GetHigh()); 720 Load32Disp(rl_address.reg, 0, rl_result.reg.GetLow()); 721 } 722 StoreValueWide(rl_dest, rl_result); 723 } else { 724 DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); 725 // Unaligned load with LDR and LDRSH is allowed on ARMv7 with SCTLR.A set to 0. 726 LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size); 727 StoreValue(rl_dest, rl_result); 728 } 729 return true; 730} 731 732bool ArmMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { 733 RegLocation rl_src_address = info->args[0]; // long address 734 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] 735 RegLocation rl_src_value = info->args[2]; // [size] value 736 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 737 if (size == k64) { 738 // Fake unaligned STRD by two unaligned STR instructions on ARMv7 with SCTLR.A set to 0. 739 RegLocation rl_value = LoadValueWide(rl_src_value, kCoreReg); 740 StoreBaseDisp(rl_address.reg, 0, rl_value.reg.GetLow(), k32); 741 StoreBaseDisp(rl_address.reg, 4, rl_value.reg.GetHigh(), k32); 742 } else { 743 DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); 744 // Unaligned store with STR and STRSH is allowed on ARMv7 with SCTLR.A set to 0. 745 RegLocation rl_value = LoadValue(rl_src_value, kCoreReg); 746 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size); 747 } 748 return true; 749} 750 751void ArmMir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { 752 LOG(FATAL) << "Unexpected use of OpLea for Arm"; 753} 754 755void ArmMir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { 756 LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm"; 757} 758 759void ArmMir2Lir::OpTlsCmp(ThreadOffset<8> offset, int val) { 760 UNIMPLEMENTED(FATAL) << "Should not be called."; 761} 762 763bool ArmMir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { 764 DCHECK_EQ(cu_->instruction_set, kThumb2); 765 // Unused - RegLocation rl_src_unsafe = info->args[0]; 766 RegLocation rl_src_obj = info->args[1]; // Object - known non-null 767 RegLocation rl_src_offset = info->args[2]; // long low 768 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] 769 RegLocation rl_src_expected = info->args[4]; // int, long or Object 770 // If is_long, high half is in info->args[5] 771 RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object 772 // If is_long, high half is in info->args[7] 773 RegLocation rl_dest = InlineTarget(info); // boolean place for result 774 775 // We have only 5 temporary registers available and actually only 4 if the InlineTarget 776 // above locked one of the temps. For a straightforward CAS64 we need 7 registers: 777 // r_ptr (1), new_value (2), expected(2) and ldrexd result (2). If neither expected nor 778 // new_value is in a non-temp core register we shall reload them in the ldrex/strex loop 779 // into the same temps, reducing the number of required temps down to 5. We shall work 780 // around the potentially locked temp by using LR for r_ptr, unconditionally. 781 // TODO: Pass information about the need for more temps to the stack frame generation 782 // code so that we can rely on being able to allocate enough temps. 783 DCHECK(!GetRegInfo(rs_rARM_LR)->IsTemp()); 784 MarkTemp(rs_rARM_LR); 785 FreeTemp(rs_rARM_LR); 786 LockTemp(rs_rARM_LR); 787 bool load_early = true; 788 if (is_long) { 789 RegStorage expected_reg = rl_src_expected.reg.IsPair() ? rl_src_expected.reg.GetLow() : 790 rl_src_expected.reg; 791 RegStorage new_val_reg = rl_src_new_value.reg.IsPair() ? rl_src_new_value.reg.GetLow() : 792 rl_src_new_value.reg; 793 bool expected_is_core_reg = rl_src_expected.location == kLocPhysReg && !expected_reg.IsFloat(); 794 bool new_value_is_core_reg = rl_src_new_value.location == kLocPhysReg && !new_val_reg.IsFloat(); 795 bool expected_is_good_reg = expected_is_core_reg && !IsTemp(expected_reg); 796 bool new_value_is_good_reg = new_value_is_core_reg && !IsTemp(new_val_reg); 797 798 if (!expected_is_good_reg && !new_value_is_good_reg) { 799 // None of expected/new_value is non-temp reg, need to load both late 800 load_early = false; 801 // Make sure they are not in the temp regs and the load will not be skipped. 802 if (expected_is_core_reg) { 803 FlushRegWide(rl_src_expected.reg); 804 ClobberSReg(rl_src_expected.s_reg_low); 805 ClobberSReg(GetSRegHi(rl_src_expected.s_reg_low)); 806 rl_src_expected.location = kLocDalvikFrame; 807 } 808 if (new_value_is_core_reg) { 809 FlushRegWide(rl_src_new_value.reg); 810 ClobberSReg(rl_src_new_value.s_reg_low); 811 ClobberSReg(GetSRegHi(rl_src_new_value.s_reg_low)); 812 rl_src_new_value.location = kLocDalvikFrame; 813 } 814 } 815 } 816 817 // Release store semantics, get the barrier out of the way. TODO: revisit 818 GenMemBarrier(kStoreLoad); 819 820 RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); 821 RegLocation rl_new_value; 822 if (!is_long) { 823 rl_new_value = LoadValue(rl_src_new_value); 824 } else if (load_early) { 825 rl_new_value = LoadValueWide(rl_src_new_value, kCoreReg); 826 } 827 828 if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { 829 // Mark card for object assuming new value is stored. 830 MarkGCCard(rl_new_value.reg, rl_object.reg); 831 } 832 833 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 834 835 RegStorage r_ptr = rs_rARM_LR; 836 OpRegRegReg(kOpAdd, r_ptr, rl_object.reg, rl_offset.reg); 837 838 // Free now unneeded rl_object and rl_offset to give more temps. 839 ClobberSReg(rl_object.s_reg_low); 840 FreeTemp(rl_object.reg); 841 ClobberSReg(rl_offset.s_reg_low); 842 FreeTemp(rl_offset.reg); 843 844 RegLocation rl_expected; 845 if (!is_long) { 846 rl_expected = LoadValue(rl_src_expected); 847 } else if (load_early) { 848 rl_expected = LoadValueWide(rl_src_expected, kCoreReg); 849 } else { 850 // NOTE: partially defined rl_expected & rl_new_value - but we just want the regs. 851 RegStorage low_reg = AllocTemp(); 852 RegStorage high_reg = AllocTemp(); 853 rl_new_value.reg = RegStorage::MakeRegPair(low_reg, high_reg); 854 rl_expected = rl_new_value; 855 } 856 857 // do { 858 // tmp = [r_ptr] - expected; 859 // } while (tmp == 0 && failure([r_ptr] <- r_new_value)); 860 // result = tmp != 0; 861 862 RegStorage r_tmp = AllocTemp(); 863 LIR* target = NewLIR0(kPseudoTargetLabel); 864 865 LIR* it = nullptr; 866 if (is_long) { 867 RegStorage r_tmp_high = AllocTemp(); 868 if (!load_early) { 869 LoadValueDirectWide(rl_src_expected, rl_expected.reg); 870 } 871 NewLIR3(kThumb2Ldrexd, r_tmp.GetReg(), r_tmp_high.GetReg(), r_ptr.GetReg()); 872 OpRegReg(kOpSub, r_tmp, rl_expected.reg.GetLow()); 873 OpRegReg(kOpSub, r_tmp_high, rl_expected.reg.GetHigh()); 874 if (!load_early) { 875 LoadValueDirectWide(rl_src_new_value, rl_new_value.reg); 876 } 877 // Make sure we use ORR that sets the ccode 878 if (r_tmp.Low8() && r_tmp_high.Low8()) { 879 NewLIR2(kThumbOrr, r_tmp.GetReg(), r_tmp_high.GetReg()); 880 } else { 881 NewLIR4(kThumb2OrrRRRs, r_tmp.GetReg(), r_tmp.GetReg(), r_tmp_high.GetReg(), 0); 882 } 883 FreeTemp(r_tmp_high); // Now unneeded 884 885 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 886 it = OpIT(kCondEq, "T"); 887 NewLIR4(kThumb2Strexd /* eq */, r_tmp.GetReg(), rl_new_value.reg.GetLowReg(), rl_new_value.reg.GetHighReg(), r_ptr.GetReg()); 888 889 } else { 890 NewLIR3(kThumb2Ldrex, r_tmp.GetReg(), r_ptr.GetReg(), 0); 891 OpRegReg(kOpSub, r_tmp, rl_expected.reg); 892 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 893 it = OpIT(kCondEq, "T"); 894 NewLIR4(kThumb2Strex /* eq */, r_tmp.GetReg(), rl_new_value.reg.GetReg(), r_ptr.GetReg(), 0); 895 } 896 897 // Still one conditional left from OpIT(kCondEq, "T") from either branch 898 OpRegImm(kOpCmp /* eq */, r_tmp, 1); 899 OpEndIT(it); 900 901 OpCondBranch(kCondEq, target); 902 903 if (!load_early) { 904 FreeTemp(rl_expected.reg); // Now unneeded. 905 } 906 907 // result := (tmp1 != 0) ? 0 : 1; 908 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 909 OpRegRegImm(kOpRsub, rl_result.reg, r_tmp, 1); 910 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 911 it = OpIT(kCondUlt, ""); 912 LoadConstant(rl_result.reg, 0); /* cc */ 913 FreeTemp(r_tmp); // Now unneeded. 914 OpEndIT(it); // Barrier to terminate OpIT. 915 916 StoreValue(rl_dest, rl_result); 917 918 // Now, restore lr to its non-temp status. 919 Clobber(rs_rARM_LR); 920 UnmarkTemp(rs_rARM_LR); 921 return true; 922} 923 924LIR* ArmMir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { 925 return RawLIR(current_dalvik_offset_, kThumb2LdrPcRel12, reg.GetReg(), 0, 0, 0, 0, target); 926} 927 928LIR* ArmMir2Lir::OpVldm(RegStorage r_base, int count) { 929 return NewLIR3(kThumb2Vldms, r_base.GetReg(), rs_fr0.GetReg(), count); 930} 931 932LIR* ArmMir2Lir::OpVstm(RegStorage r_base, int count) { 933 return NewLIR3(kThumb2Vstms, r_base.GetReg(), rs_fr0.GetReg(), count); 934} 935 936void ArmMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 937 RegLocation rl_result, int lit, 938 int first_bit, int second_bit) { 939 OpRegRegRegShift(kOpAdd, rl_result.reg, rl_src.reg, rl_src.reg, 940 EncodeShift(kArmLsl, second_bit - first_bit)); 941 if (first_bit != 0) { 942 OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); 943 } 944} 945 946void ArmMir2Lir::GenDivZeroCheckWide(RegStorage reg) { 947 DCHECK(reg.IsPair()); // TODO: support k64BitSolo. 948 RegStorage t_reg = AllocTemp(); 949 NewLIR4(kThumb2OrrRRRs, t_reg.GetReg(), reg.GetLowReg(), reg.GetHighReg(), 0); 950 FreeTemp(t_reg); 951 GenDivZeroCheck(kCondEq); 952} 953 954// Test suspend flag, return target of taken suspend branch 955LIR* ArmMir2Lir::OpTestSuspend(LIR* target) { 956#ifdef ARM_R4_SUSPEND_FLAG 957 NewLIR2(kThumbSubRI8, rs_rARM_SUSPEND.GetReg(), 1); 958 return OpCondBranch((target == NULL) ? kCondEq : kCondNe, target); 959#else 960 RegStorage t_reg = AllocTemp(); 961 LoadBaseDisp(rs_rARM_SELF, Thread::ThreadFlagsOffset<4>().Int32Value(), 962 t_reg, kUnsignedHalf); 963 LIR* cmp_branch = OpCmpImmBranch((target == NULL) ? kCondNe : kCondEq, t_reg, 964 0, target); 965 FreeTemp(t_reg); 966 return cmp_branch; 967#endif 968} 969 970// Decrement register and branch on condition 971LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { 972 // Combine sub & test using sub setflags encoding here 973 OpRegRegImm(kOpSub, reg, reg, 1); // For value == 1, this should set flags. 974 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 975 return OpCondBranch(c_code, target); 976} 977 978bool ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 979#if ANDROID_SMP != 0 980 // Start off with using the last LIR as the barrier. If it is not enough, then we will generate one. 981 LIR* barrier = last_lir_insn_; 982 983 int dmb_flavor; 984 // TODO: revisit Arm barrier kinds 985 switch (barrier_kind) { 986 case kLoadStore: dmb_flavor = kISH; break; 987 case kLoadLoad: dmb_flavor = kISH; break; 988 case kStoreStore: dmb_flavor = kISHST; break; 989 case kStoreLoad: dmb_flavor = kISH; break; 990 default: 991 LOG(FATAL) << "Unexpected MemBarrierKind: " << barrier_kind; 992 dmb_flavor = kSY; // quiet gcc. 993 break; 994 } 995 996 bool ret = false; 997 998 // If the same barrier already exists, don't generate another. 999 if (barrier == nullptr 1000 || (barrier != nullptr && (barrier->opcode != kThumb2Dmb || barrier->operands[0] != dmb_flavor))) { 1001 barrier = NewLIR1(kThumb2Dmb, dmb_flavor); 1002 ret = true; 1003 } 1004 1005 // At this point we must have a memory barrier. Mark it as a scheduling barrier as well. 1006 DCHECK(!barrier->flags.use_def_invalid); 1007 barrier->u.m.def_mask = &kEncodeAll; 1008 return ret; 1009#else 1010 return false; 1011#endif 1012} 1013 1014void ArmMir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) { 1015 LOG(FATAL) << "Unexpected use GenNotLong()"; 1016} 1017 1018void ArmMir2Lir::GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1019 RegLocation rl_src2, bool is_div) { 1020 LOG(FATAL) << "Unexpected use GenDivRemLong()"; 1021} 1022 1023void ArmMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { 1024 rl_src = LoadValueWide(rl_src, kCoreReg); 1025 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1026 RegStorage z_reg = AllocTemp(); 1027 LoadConstantNoClobber(z_reg, 0); 1028 // Check for destructive overlap 1029 if (rl_result.reg.GetLowReg() == rl_src.reg.GetHighReg()) { 1030 RegStorage t_reg = AllocTemp(); 1031 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow()); 1032 OpRegRegReg(kOpSbc, rl_result.reg.GetHigh(), z_reg, t_reg); 1033 FreeTemp(t_reg); 1034 } else { 1035 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow()); 1036 OpRegRegReg(kOpSbc, rl_result.reg.GetHigh(), z_reg, rl_src.reg.GetHigh()); 1037 } 1038 FreeTemp(z_reg); 1039 StoreValueWide(rl_dest, rl_result); 1040} 1041 1042void ArmMir2Lir::GenMulLong(Instruction::Code opcode, RegLocation rl_dest, 1043 RegLocation rl_src1, RegLocation rl_src2) { 1044 /* 1045 * tmp1 = src1.hi * src2.lo; // src1.hi is no longer needed 1046 * dest = src1.lo * src2.lo; 1047 * tmp1 += src1.lo * src2.hi; 1048 * dest.hi += tmp1; 1049 * 1050 * To pull off inline multiply, we have a worst-case requirement of 7 temporary 1051 * registers. Normally for Arm, we get 5. We can get to 6 by including 1052 * lr in the temp set. The only problematic case is all operands and result are 1053 * distinct, and none have been promoted. In that case, we can succeed by aggressively 1054 * freeing operand temp registers after they are no longer needed. All other cases 1055 * can proceed normally. We'll just punt on the case of the result having a misaligned 1056 * overlap with either operand and send that case to a runtime handler. 1057 */ 1058 RegLocation rl_result; 1059 if (BadOverlap(rl_src1, rl_dest) || (BadOverlap(rl_src2, rl_dest))) { 1060 ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pLmul); 1061 FlushAllRegs(); 1062 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 1063 rl_result = GetReturnWide(kCoreReg); 1064 StoreValueWide(rl_dest, rl_result); 1065 return; 1066 } 1067 1068 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1069 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1070 1071 int reg_status = 0; 1072 RegStorage res_lo; 1073 RegStorage res_hi; 1074 bool dest_promoted = rl_dest.location == kLocPhysReg && rl_dest.reg.Valid() && 1075 !IsTemp(rl_dest.reg.GetLow()) && !IsTemp(rl_dest.reg.GetHigh()); 1076 bool src1_promoted = !IsTemp(rl_src1.reg.GetLow()) && !IsTemp(rl_src1.reg.GetHigh()); 1077 bool src2_promoted = !IsTemp(rl_src2.reg.GetLow()) && !IsTemp(rl_src2.reg.GetHigh()); 1078 // Check if rl_dest is *not* either operand and we have enough temp registers. 1079 if ((rl_dest.s_reg_low != rl_src1.s_reg_low && rl_dest.s_reg_low != rl_src2.s_reg_low) && 1080 (dest_promoted || src1_promoted || src2_promoted)) { 1081 // In this case, we do not need to manually allocate temp registers for result. 1082 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1083 res_lo = rl_result.reg.GetLow(); 1084 res_hi = rl_result.reg.GetHigh(); 1085 } else { 1086 res_lo = AllocTemp(); 1087 if ((rl_src1.s_reg_low == rl_src2.s_reg_low) || src1_promoted || src2_promoted) { 1088 // In this case, we have enough temp registers to be allocated for result. 1089 res_hi = AllocTemp(); 1090 reg_status = 1; 1091 } else { 1092 // In this case, all temps are now allocated. 1093 // res_hi will be allocated after we can free src1_hi. 1094 reg_status = 2; 1095 } 1096 } 1097 1098 // Temporarily add LR to the temp pool, and assign it to tmp1 1099 MarkTemp(rs_rARM_LR); 1100 FreeTemp(rs_rARM_LR); 1101 RegStorage tmp1 = rs_rARM_LR; 1102 LockTemp(rs_rARM_LR); 1103 1104 if (rl_src1.reg == rl_src2.reg) { 1105 DCHECK(res_hi.Valid()); 1106 DCHECK(res_lo.Valid()); 1107 NewLIR3(kThumb2MulRRR, tmp1.GetReg(), rl_src1.reg.GetLowReg(), rl_src1.reg.GetHighReg()); 1108 NewLIR4(kThumb2Umull, res_lo.GetReg(), res_hi.GetReg(), rl_src1.reg.GetLowReg(), 1109 rl_src1.reg.GetLowReg()); 1110 OpRegRegRegShift(kOpAdd, res_hi, res_hi, tmp1, EncodeShift(kArmLsl, 1)); 1111 } else { 1112 NewLIR3(kThumb2MulRRR, tmp1.GetReg(), rl_src2.reg.GetLowReg(), rl_src1.reg.GetHighReg()); 1113 if (reg_status == 2) { 1114 DCHECK(!res_hi.Valid()); 1115 DCHECK_NE(rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg()); 1116 DCHECK_NE(rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg()); 1117 // Will force free src1_hi, so must clobber. 1118 Clobber(rl_src1.reg); 1119 FreeTemp(rl_src1.reg.GetHigh()); 1120 res_hi = AllocTemp(); 1121 } 1122 DCHECK(res_hi.Valid()); 1123 DCHECK(res_lo.Valid()); 1124 NewLIR4(kThumb2Umull, res_lo.GetReg(), res_hi.GetReg(), rl_src2.reg.GetLowReg(), 1125 rl_src1.reg.GetLowReg()); 1126 NewLIR4(kThumb2Mla, tmp1.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetHighReg(), 1127 tmp1.GetReg()); 1128 NewLIR4(kThumb2AddRRR, res_hi.GetReg(), tmp1.GetReg(), res_hi.GetReg(), 0); 1129 if (reg_status == 2) { 1130 FreeTemp(rl_src1.reg.GetLow()); 1131 } 1132 } 1133 1134 // Now, restore lr to its non-temp status. 1135 FreeTemp(tmp1); 1136 Clobber(rs_rARM_LR); 1137 UnmarkTemp(rs_rARM_LR); 1138 1139 if (reg_status != 0) { 1140 // We had manually allocated registers for rl_result. 1141 // Now construct a RegLocation. 1142 rl_result = GetReturnWide(kCoreReg); // Just using as a template. 1143 rl_result.reg = RegStorage::MakeRegPair(res_lo, res_hi); 1144 } 1145 1146 StoreValueWide(rl_dest, rl_result); 1147} 1148 1149void ArmMir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 1150 RegLocation rl_src2) { 1151 LOG(FATAL) << "Unexpected use of GenAddLong for Arm"; 1152} 1153 1154void ArmMir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 1155 RegLocation rl_src2) { 1156 LOG(FATAL) << "Unexpected use of GenSubLong for Arm"; 1157} 1158 1159void ArmMir2Lir::GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 1160 RegLocation rl_src2) { 1161 LOG(FATAL) << "Unexpected use of GenAndLong for Arm"; 1162} 1163 1164void ArmMir2Lir::GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 1165 RegLocation rl_src2) { 1166 LOG(FATAL) << "Unexpected use of GenOrLong for Arm"; 1167} 1168 1169void ArmMir2Lir::GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 1170 RegLocation rl_src2) { 1171 LOG(FATAL) << "Unexpected use of genXoLong for Arm"; 1172} 1173 1174/* 1175 * Generate array load 1176 */ 1177void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1178 RegLocation rl_index, RegLocation rl_dest, int scale) { 1179 RegisterClass reg_class = RegClassBySize(size); 1180 int len_offset = mirror::Array::LengthOffset().Int32Value(); 1181 int data_offset; 1182 RegLocation rl_result; 1183 bool constant_index = rl_index.is_const; 1184 rl_array = LoadValue(rl_array, kRefReg); 1185 if (!constant_index) { 1186 rl_index = LoadValue(rl_index, kCoreReg); 1187 } 1188 1189 if (rl_dest.wide) { 1190 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 1191 } else { 1192 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 1193 } 1194 1195 // If index is constant, just fold it into the data offset 1196 if (constant_index) { 1197 data_offset += mir_graph_->ConstantValue(rl_index) << scale; 1198 } 1199 1200 /* null object? */ 1201 GenNullCheck(rl_array.reg, opt_flags); 1202 1203 bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); 1204 RegStorage reg_len; 1205 if (needs_range_check) { 1206 reg_len = AllocTemp(); 1207 /* Get len */ 1208 Load32Disp(rl_array.reg, len_offset, reg_len); 1209 MarkPossibleNullPointerException(opt_flags); 1210 } else { 1211 ForceImplicitNullCheck(rl_array.reg, opt_flags); 1212 } 1213 if (rl_dest.wide || rl_dest.fp || constant_index) { 1214 RegStorage reg_ptr; 1215 if (constant_index) { 1216 reg_ptr = rl_array.reg; // NOTE: must not alter reg_ptr in constant case. 1217 } else { 1218 // No special indexed operation, lea + load w/ displacement 1219 reg_ptr = AllocTempRef(); 1220 OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.reg, rl_index.reg, EncodeShift(kArmLsl, scale)); 1221 FreeTemp(rl_index.reg); 1222 } 1223 rl_result = EvalLoc(rl_dest, reg_class, true); 1224 1225 if (needs_range_check) { 1226 if (constant_index) { 1227 GenArrayBoundsCheck(mir_graph_->ConstantValue(rl_index), reg_len); 1228 } else { 1229 GenArrayBoundsCheck(rl_index.reg, reg_len); 1230 } 1231 FreeTemp(reg_len); 1232 } 1233 LoadBaseDisp(reg_ptr, data_offset, rl_result.reg, size); 1234 MarkPossibleNullPointerException(opt_flags); 1235 if (!constant_index) { 1236 FreeTemp(reg_ptr); 1237 } 1238 if (rl_dest.wide) { 1239 StoreValueWide(rl_dest, rl_result); 1240 } else { 1241 StoreValue(rl_dest, rl_result); 1242 } 1243 } else { 1244 // Offset base, then use indexed load 1245 RegStorage reg_ptr = AllocTempRef(); 1246 OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset); 1247 FreeTemp(rl_array.reg); 1248 rl_result = EvalLoc(rl_dest, reg_class, true); 1249 1250 if (needs_range_check) { 1251 GenArrayBoundsCheck(rl_index.reg, reg_len); 1252 FreeTemp(reg_len); 1253 } 1254 LoadBaseIndexed(reg_ptr, rl_index.reg, rl_result.reg, scale, size); 1255 MarkPossibleNullPointerException(opt_flags); 1256 FreeTemp(reg_ptr); 1257 StoreValue(rl_dest, rl_result); 1258 } 1259} 1260 1261/* 1262 * Generate array store 1263 * 1264 */ 1265void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1266 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { 1267 RegisterClass reg_class = RegClassBySize(size); 1268 int len_offset = mirror::Array::LengthOffset().Int32Value(); 1269 bool constant_index = rl_index.is_const; 1270 1271 int data_offset; 1272 if (size == k64 || size == kDouble) { 1273 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 1274 } else { 1275 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 1276 } 1277 1278 // If index is constant, just fold it into the data offset. 1279 if (constant_index) { 1280 data_offset += mir_graph_->ConstantValue(rl_index) << scale; 1281 } 1282 1283 rl_array = LoadValue(rl_array, kRefReg); 1284 if (!constant_index) { 1285 rl_index = LoadValue(rl_index, kCoreReg); 1286 } 1287 1288 RegStorage reg_ptr; 1289 bool allocated_reg_ptr_temp = false; 1290 if (constant_index) { 1291 reg_ptr = rl_array.reg; 1292 } else if (IsTemp(rl_array.reg) && !card_mark) { 1293 Clobber(rl_array.reg); 1294 reg_ptr = rl_array.reg; 1295 } else { 1296 allocated_reg_ptr_temp = true; 1297 reg_ptr = AllocTempRef(); 1298 } 1299 1300 /* null object? */ 1301 GenNullCheck(rl_array.reg, opt_flags); 1302 1303 bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); 1304 RegStorage reg_len; 1305 if (needs_range_check) { 1306 reg_len = AllocTemp(); 1307 // NOTE: max live temps(4) here. 1308 /* Get len */ 1309 Load32Disp(rl_array.reg, len_offset, reg_len); 1310 MarkPossibleNullPointerException(opt_flags); 1311 } else { 1312 ForceImplicitNullCheck(rl_array.reg, opt_flags); 1313 } 1314 /* at this point, reg_ptr points to array, 2 live temps */ 1315 if (rl_src.wide || rl_src.fp || constant_index) { 1316 if (rl_src.wide) { 1317 rl_src = LoadValueWide(rl_src, reg_class); 1318 } else { 1319 rl_src = LoadValue(rl_src, reg_class); 1320 } 1321 if (!constant_index) { 1322 OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.reg, rl_index.reg, EncodeShift(kArmLsl, scale)); 1323 } 1324 if (needs_range_check) { 1325 if (constant_index) { 1326 GenArrayBoundsCheck(mir_graph_->ConstantValue(rl_index), reg_len); 1327 } else { 1328 GenArrayBoundsCheck(rl_index.reg, reg_len); 1329 } 1330 FreeTemp(reg_len); 1331 } 1332 1333 StoreBaseDisp(reg_ptr, data_offset, rl_src.reg, size); 1334 MarkPossibleNullPointerException(opt_flags); 1335 } else { 1336 /* reg_ptr -> array data */ 1337 OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset); 1338 rl_src = LoadValue(rl_src, reg_class); 1339 if (needs_range_check) { 1340 GenArrayBoundsCheck(rl_index.reg, reg_len); 1341 FreeTemp(reg_len); 1342 } 1343 StoreBaseIndexed(reg_ptr, rl_index.reg, rl_src.reg, scale, size); 1344 MarkPossibleNullPointerException(opt_flags); 1345 } 1346 if (allocated_reg_ptr_temp) { 1347 FreeTemp(reg_ptr); 1348 } 1349 if (card_mark) { 1350 MarkGCCard(rl_src.reg, rl_array.reg); 1351 } 1352} 1353 1354 1355void ArmMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, 1356 RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift) { 1357 rl_src = LoadValueWide(rl_src, kCoreReg); 1358 // Per spec, we only care about low 6 bits of shift amount. 1359 int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; 1360 if (shift_amount == 0) { 1361 StoreValueWide(rl_dest, rl_src); 1362 return; 1363 } 1364 if (BadOverlap(rl_src, rl_dest)) { 1365 GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); 1366 return; 1367 } 1368 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1369 switch (opcode) { 1370 case Instruction::SHL_LONG: 1371 case Instruction::SHL_LONG_2ADDR: 1372 if (shift_amount == 1) { 1373 OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src.reg.GetLow(), rl_src.reg.GetLow()); 1374 OpRegRegReg(kOpAdc, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), rl_src.reg.GetHigh()); 1375 } else if (shift_amount == 32) { 1376 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg); 1377 LoadConstant(rl_result.reg.GetLow(), 0); 1378 } else if (shift_amount > 31) { 1379 OpRegRegImm(kOpLsl, rl_result.reg.GetHigh(), rl_src.reg.GetLow(), shift_amount - 32); 1380 LoadConstant(rl_result.reg.GetLow(), 0); 1381 } else { 1382 OpRegRegImm(kOpLsl, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount); 1383 OpRegRegRegShift(kOpOr, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), rl_src.reg.GetLow(), 1384 EncodeShift(kArmLsr, 32 - shift_amount)); 1385 OpRegRegImm(kOpLsl, rl_result.reg.GetLow(), rl_src.reg.GetLow(), shift_amount); 1386 } 1387 break; 1388 case Instruction::SHR_LONG: 1389 case Instruction::SHR_LONG_2ADDR: 1390 if (shift_amount == 32) { 1391 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1392 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), 31); 1393 } else if (shift_amount > 31) { 1394 OpRegRegImm(kOpAsr, rl_result.reg.GetLow(), rl_src.reg.GetHigh(), shift_amount - 32); 1395 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), 31); 1396 } else { 1397 RegStorage t_reg = AllocTemp(); 1398 OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetLow(), shift_amount); 1399 OpRegRegRegShift(kOpOr, rl_result.reg.GetLow(), t_reg, rl_src.reg.GetHigh(), 1400 EncodeShift(kArmLsl, 32 - shift_amount)); 1401 FreeTemp(t_reg); 1402 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount); 1403 } 1404 break; 1405 case Instruction::USHR_LONG: 1406 case Instruction::USHR_LONG_2ADDR: 1407 if (shift_amount == 32) { 1408 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1409 LoadConstant(rl_result.reg.GetHigh(), 0); 1410 } else if (shift_amount > 31) { 1411 OpRegRegImm(kOpLsr, rl_result.reg.GetLow(), rl_src.reg.GetHigh(), shift_amount - 32); 1412 LoadConstant(rl_result.reg.GetHigh(), 0); 1413 } else { 1414 RegStorage t_reg = AllocTemp(); 1415 OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetLow(), shift_amount); 1416 OpRegRegRegShift(kOpOr, rl_result.reg.GetLow(), t_reg, rl_src.reg.GetHigh(), 1417 EncodeShift(kArmLsl, 32 - shift_amount)); 1418 FreeTemp(t_reg); 1419 OpRegRegImm(kOpLsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount); 1420 } 1421 break; 1422 default: 1423 LOG(FATAL) << "Unexpected case"; 1424 } 1425 StoreValueWide(rl_dest, rl_result); 1426} 1427 1428void ArmMir2Lir::GenArithImmOpLong(Instruction::Code opcode, 1429 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 1430 if ((opcode == Instruction::SUB_LONG_2ADDR) || (opcode == Instruction::SUB_LONG)) { 1431 if (!rl_src2.is_const) { 1432 // Don't bother with special handling for subtract from immediate. 1433 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 1434 return; 1435 } 1436 } else { 1437 // Normalize 1438 if (!rl_src2.is_const) { 1439 DCHECK(rl_src1.is_const); 1440 std::swap(rl_src1, rl_src2); 1441 } 1442 } 1443 if (BadOverlap(rl_src1, rl_dest)) { 1444 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 1445 return; 1446 } 1447 DCHECK(rl_src2.is_const); 1448 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 1449 uint32_t val_lo = Low32Bits(val); 1450 uint32_t val_hi = High32Bits(val); 1451 int32_t mod_imm_lo = ModifiedImmediate(val_lo); 1452 int32_t mod_imm_hi = ModifiedImmediate(val_hi); 1453 1454 // Only a subset of add/sub immediate instructions set carry - so bail if we don't fit 1455 switch (opcode) { 1456 case Instruction::ADD_LONG: 1457 case Instruction::ADD_LONG_2ADDR: 1458 case Instruction::SUB_LONG: 1459 case Instruction::SUB_LONG_2ADDR: 1460 if ((mod_imm_lo < 0) || (mod_imm_hi < 0)) { 1461 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 1462 return; 1463 } 1464 break; 1465 default: 1466 break; 1467 } 1468 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1469 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1470 // NOTE: once we've done the EvalLoc on dest, we can no longer bail. 1471 switch (opcode) { 1472 case Instruction::ADD_LONG: 1473 case Instruction::ADD_LONG_2ADDR: 1474 NewLIR3(kThumb2AddRRI8M, rl_result.reg.GetLowReg(), rl_src1.reg.GetLowReg(), mod_imm_lo); 1475 NewLIR3(kThumb2AdcRRI8M, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), mod_imm_hi); 1476 break; 1477 case Instruction::OR_LONG: 1478 case Instruction::OR_LONG_2ADDR: 1479 if ((val_lo != 0) || (rl_result.reg.GetLowReg() != rl_src1.reg.GetLowReg())) { 1480 OpRegRegImm(kOpOr, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo); 1481 } 1482 if ((val_hi != 0) || (rl_result.reg.GetHighReg() != rl_src1.reg.GetHighReg())) { 1483 OpRegRegImm(kOpOr, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi); 1484 } 1485 break; 1486 case Instruction::XOR_LONG: 1487 case Instruction::XOR_LONG_2ADDR: 1488 OpRegRegImm(kOpXor, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo); 1489 OpRegRegImm(kOpXor, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi); 1490 break; 1491 case Instruction::AND_LONG: 1492 case Instruction::AND_LONG_2ADDR: 1493 if ((val_lo != 0xffffffff) || (rl_result.reg.GetLowReg() != rl_src1.reg.GetLowReg())) { 1494 OpRegRegImm(kOpAnd, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo); 1495 } 1496 if ((val_hi != 0xffffffff) || (rl_result.reg.GetHighReg() != rl_src1.reg.GetHighReg())) { 1497 OpRegRegImm(kOpAnd, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi); 1498 } 1499 break; 1500 case Instruction::SUB_LONG_2ADDR: 1501 case Instruction::SUB_LONG: 1502 NewLIR3(kThumb2SubRRI8M, rl_result.reg.GetLowReg(), rl_src1.reg.GetLowReg(), mod_imm_lo); 1503 NewLIR3(kThumb2SbcRRI8M, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), mod_imm_hi); 1504 break; 1505 default: 1506 LOG(FATAL) << "Unexpected opcode " << opcode; 1507 } 1508 StoreValueWide(rl_dest, rl_result); 1509} 1510 1511} // namespace art 1512