utility_arm.cc revision 332b7aa6220124dc638b9f7e59611c376473f128
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "arm_lir.h" 18#include "codegen_arm.h" 19#include "dex/quick/mir_to_lir-inl.h" 20 21namespace art { 22 23/* This file contains codegen for the Thumb ISA. */ 24 25static int32_t EncodeImmSingle(int32_t value) { 26 int32_t res; 27 int32_t bit_a = (value & 0x80000000) >> 31; 28 int32_t not_bit_b = (value & 0x40000000) >> 30; 29 int32_t bit_b = (value & 0x20000000) >> 29; 30 int32_t b_smear = (value & 0x3e000000) >> 25; 31 int32_t slice = (value & 0x01f80000) >> 19; 32 int32_t zeroes = (value & 0x0007ffff); 33 if (zeroes != 0) 34 return -1; 35 if (bit_b) { 36 if ((not_bit_b != 0) || (b_smear != 0x1f)) 37 return -1; 38 } else { 39 if ((not_bit_b != 1) || (b_smear != 0x0)) 40 return -1; 41 } 42 res = (bit_a << 7) | (bit_b << 6) | slice; 43 return res; 44} 45 46/* 47 * Determine whether value can be encoded as a Thumb2 floating point 48 * immediate. If not, return -1. If so return encoded 8-bit value. 49 */ 50static int32_t EncodeImmDouble(int64_t value) { 51 int32_t res; 52 int32_t bit_a = (value & 0x8000000000000000ll) >> 63; 53 int32_t not_bit_b = (value & 0x4000000000000000ll) >> 62; 54 int32_t bit_b = (value & 0x2000000000000000ll) >> 61; 55 int32_t b_smear = (value & 0x3fc0000000000000ll) >> 54; 56 int32_t slice = (value & 0x003f000000000000ll) >> 48; 57 uint64_t zeroes = (value & 0x0000ffffffffffffll); 58 if (zeroes != 0ull) 59 return -1; 60 if (bit_b) { 61 if ((not_bit_b != 0) || (b_smear != 0xff)) 62 return -1; 63 } else { 64 if ((not_bit_b != 1) || (b_smear != 0x0)) 65 return -1; 66 } 67 res = (bit_a << 7) | (bit_b << 6) | slice; 68 return res; 69} 70 71LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) { 72 DCHECK(ARM_SINGLEREG(r_dest)); 73 if (value == 0) { 74 // TODO: we need better info about the target CPU. a vector exclusive or 75 // would probably be better here if we could rely on its existance. 76 // Load an immediate +2.0 (which encodes to 0) 77 NewLIR2(kThumb2Vmovs_IMM8, r_dest, 0); 78 // +0.0 = +2.0 - +2.0 79 return NewLIR3(kThumb2Vsubs, r_dest, r_dest, r_dest); 80 } else { 81 int encoded_imm = EncodeImmSingle(value); 82 if (encoded_imm >= 0) { 83 return NewLIR2(kThumb2Vmovs_IMM8, r_dest, encoded_imm); 84 } 85 } 86 LIR* data_target = ScanLiteralPool(literal_list_, value, 0); 87 if (data_target == NULL) { 88 data_target = AddWordData(&literal_list_, value); 89 } 90 LIR* load_pc_rel = RawLIR(current_dalvik_offset_, kThumb2Vldrs, 91 r_dest, r15pc, 0, 0, 0, data_target); 92 SetMemRefType(load_pc_rel, true, kLiteral); 93 AppendLIR(load_pc_rel); 94 return load_pc_rel; 95} 96 97static int LeadingZeros(uint32_t val) { 98 uint32_t alt; 99 int32_t n; 100 int32_t count; 101 102 count = 16; 103 n = 32; 104 do { 105 alt = val >> count; 106 if (alt != 0) { 107 n = n - count; 108 val = alt; 109 } 110 count >>= 1; 111 } while (count); 112 return n - val; 113} 114 115/* 116 * Determine whether value can be encoded as a Thumb2 modified 117 * immediate. If not, return -1. If so, return i:imm3:a:bcdefgh form. 118 */ 119int ArmMir2Lir::ModifiedImmediate(uint32_t value) { 120 int32_t z_leading; 121 int32_t z_trailing; 122 uint32_t b0 = value & 0xff; 123 124 /* Note: case of value==0 must use 0:000:0:0000000 encoding */ 125 if (value <= 0xFF) 126 return b0; // 0:000:a:bcdefgh 127 if (value == ((b0 << 16) | b0)) 128 return (0x1 << 8) | b0; /* 0:001:a:bcdefgh */ 129 if (value == ((b0 << 24) | (b0 << 16) | (b0 << 8) | b0)) 130 return (0x3 << 8) | b0; /* 0:011:a:bcdefgh */ 131 b0 = (value >> 8) & 0xff; 132 if (value == ((b0 << 24) | (b0 << 8))) 133 return (0x2 << 8) | b0; /* 0:010:a:bcdefgh */ 134 /* Can we do it with rotation? */ 135 z_leading = LeadingZeros(value); 136 z_trailing = 32 - LeadingZeros(~value & (value - 1)); 137 /* A run of eight or fewer active bits? */ 138 if ((z_leading + z_trailing) < 24) 139 return -1; /* No - bail */ 140 /* left-justify the constant, discarding msb (known to be 1) */ 141 value <<= z_leading + 1; 142 /* Create bcdefgh */ 143 value >>= 25; 144 /* Put it all together */ 145 return value | ((0x8 + z_leading) << 7); /* [01000..11111]:bcdefgh */ 146} 147 148bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) { 149 return (ModifiedImmediate(value) >= 0) || (ModifiedImmediate(~value) >= 0); 150} 151 152bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value) { 153 return EncodeImmSingle(value) >= 0; 154} 155 156bool ArmMir2Lir::InexpensiveConstantLong(int64_t value) { 157 return InexpensiveConstantInt(High32Bits(value)) && InexpensiveConstantInt(Low32Bits(value)); 158} 159 160bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value) { 161 return EncodeImmDouble(value) >= 0; 162} 163 164/* 165 * Load a immediate using a shortcut if possible; otherwise 166 * grab from the per-translation literal pool. 167 * 168 * No additional register clobbering operation performed. Use this version when 169 * 1) r_dest is freshly returned from AllocTemp or 170 * 2) The codegen is under fixed register usage 171 */ 172LIR* ArmMir2Lir::LoadConstantNoClobber(int r_dest, int value) { 173 LIR* res; 174 int mod_imm; 175 176 if (ARM_FPREG(r_dest)) { 177 return LoadFPConstantValue(r_dest, value); 178 } 179 180 /* See if the value can be constructed cheaply */ 181 if (ARM_LOWREG(r_dest) && (value >= 0) && (value <= 255)) { 182 return NewLIR2(kThumbMovImm, r_dest, value); 183 } 184 /* Check Modified immediate special cases */ 185 mod_imm = ModifiedImmediate(value); 186 if (mod_imm >= 0) { 187 res = NewLIR2(kThumb2MovI8M, r_dest, mod_imm); 188 return res; 189 } 190 mod_imm = ModifiedImmediate(~value); 191 if (mod_imm >= 0) { 192 res = NewLIR2(kThumb2MvnI8M, r_dest, mod_imm); 193 return res; 194 } 195 /* 16-bit immediate? */ 196 if ((value & 0xffff) == value) { 197 res = NewLIR2(kThumb2MovImm16, r_dest, value); 198 return res; 199 } 200 /* Do a low/high pair */ 201 res = NewLIR2(kThumb2MovImm16, r_dest, Low16Bits(value)); 202 NewLIR2(kThumb2MovImm16H, r_dest, High16Bits(value)); 203 return res; 204} 205 206LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) { 207 LIR* res = NewLIR1(kThumbBUncond, 0 /* offset to be patched during assembly*/); 208 res->target = target; 209 return res; 210} 211 212LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { 213 LIR* branch = NewLIR2(kThumb2BCond, 0 /* offset to be patched */, 214 ArmConditionEncoding(cc)); 215 branch->target = target; 216 return branch; 217} 218 219LIR* ArmMir2Lir::OpReg(OpKind op, int r_dest_src) { 220 ArmOpcode opcode = kThumbBkpt; 221 switch (op) { 222 case kOpBlx: 223 opcode = kThumbBlxR; 224 break; 225 default: 226 LOG(FATAL) << "Bad opcode " << op; 227 } 228 return NewLIR1(opcode, r_dest_src); 229} 230 231LIR* ArmMir2Lir::OpRegRegShift(OpKind op, int r_dest_src1, int r_src2, 232 int shift) { 233 bool thumb_form = ((shift == 0) && ARM_LOWREG(r_dest_src1) && ARM_LOWREG(r_src2)); 234 ArmOpcode opcode = kThumbBkpt; 235 switch (op) { 236 case kOpAdc: 237 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR; 238 break; 239 case kOpAnd: 240 opcode = (thumb_form) ? kThumbAndRR : kThumb2AndRRR; 241 break; 242 case kOpBic: 243 opcode = (thumb_form) ? kThumbBicRR : kThumb2BicRRR; 244 break; 245 case kOpCmn: 246 DCHECK_EQ(shift, 0); 247 opcode = (thumb_form) ? kThumbCmnRR : kThumb2CmnRR; 248 break; 249 case kOpCmp: 250 if (thumb_form) 251 opcode = kThumbCmpRR; 252 else if ((shift == 0) && !ARM_LOWREG(r_dest_src1) && !ARM_LOWREG(r_src2)) 253 opcode = kThumbCmpHH; 254 else if ((shift == 0) && ARM_LOWREG(r_dest_src1)) 255 opcode = kThumbCmpLH; 256 else if (shift == 0) 257 opcode = kThumbCmpHL; 258 else 259 opcode = kThumb2CmpRR; 260 break; 261 case kOpXor: 262 opcode = (thumb_form) ? kThumbEorRR : kThumb2EorRRR; 263 break; 264 case kOpMov: 265 DCHECK_EQ(shift, 0); 266 if (ARM_LOWREG(r_dest_src1) && ARM_LOWREG(r_src2)) 267 opcode = kThumbMovRR; 268 else if (!ARM_LOWREG(r_dest_src1) && !ARM_LOWREG(r_src2)) 269 opcode = kThumbMovRR_H2H; 270 else if (ARM_LOWREG(r_dest_src1)) 271 opcode = kThumbMovRR_H2L; 272 else 273 opcode = kThumbMovRR_L2H; 274 break; 275 case kOpMul: 276 DCHECK_EQ(shift, 0); 277 opcode = (thumb_form) ? kThumbMul : kThumb2MulRRR; 278 break; 279 case kOpMvn: 280 opcode = (thumb_form) ? kThumbMvn : kThumb2MnvRR; 281 break; 282 case kOpNeg: 283 DCHECK_EQ(shift, 0); 284 opcode = (thumb_form) ? kThumbNeg : kThumb2NegRR; 285 break; 286 case kOpOr: 287 opcode = (thumb_form) ? kThumbOrr : kThumb2OrrRRR; 288 break; 289 case kOpSbc: 290 opcode = (thumb_form) ? kThumbSbc : kThumb2SbcRRR; 291 break; 292 case kOpTst: 293 opcode = (thumb_form) ? kThumbTst : kThumb2TstRR; 294 break; 295 case kOpLsl: 296 DCHECK_EQ(shift, 0); 297 opcode = (thumb_form) ? kThumbLslRR : kThumb2LslRRR; 298 break; 299 case kOpLsr: 300 DCHECK_EQ(shift, 0); 301 opcode = (thumb_form) ? kThumbLsrRR : kThumb2LsrRRR; 302 break; 303 case kOpAsr: 304 DCHECK_EQ(shift, 0); 305 opcode = (thumb_form) ? kThumbAsrRR : kThumb2AsrRRR; 306 break; 307 case kOpRor: 308 DCHECK_EQ(shift, 0); 309 opcode = (thumb_form) ? kThumbRorRR : kThumb2RorRRR; 310 break; 311 case kOpAdd: 312 opcode = (thumb_form) ? kThumbAddRRR : kThumb2AddRRR; 313 break; 314 case kOpSub: 315 opcode = (thumb_form) ? kThumbSubRRR : kThumb2SubRRR; 316 break; 317 case kOpRev: 318 DCHECK_EQ(shift, 0); 319 if (!thumb_form) { 320 // Binary, but rm is encoded twice. 321 return NewLIR3(kThumb2RevRR, r_dest_src1, r_src2, r_src2); 322 } 323 opcode = kThumbRev; 324 break; 325 case kOpRevsh: 326 DCHECK_EQ(shift, 0); 327 if (!thumb_form) { 328 // Binary, but rm is encoded twice. 329 return NewLIR3(kThumb2RevshRR, r_dest_src1, r_src2, r_src2); 330 } 331 opcode = kThumbRevsh; 332 break; 333 case kOp2Byte: 334 DCHECK_EQ(shift, 0); 335 return NewLIR4(kThumb2Sbfx, r_dest_src1, r_src2, 0, 8); 336 case kOp2Short: 337 DCHECK_EQ(shift, 0); 338 return NewLIR4(kThumb2Sbfx, r_dest_src1, r_src2, 0, 16); 339 case kOp2Char: 340 DCHECK_EQ(shift, 0); 341 return NewLIR4(kThumb2Ubfx, r_dest_src1, r_src2, 0, 16); 342 default: 343 LOG(FATAL) << "Bad opcode: " << op; 344 break; 345 } 346 DCHECK(!IsPseudoLirOp(opcode)); 347 if (EncodingMap[opcode].flags & IS_BINARY_OP) { 348 return NewLIR2(opcode, r_dest_src1, r_src2); 349 } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { 350 if (EncodingMap[opcode].field_loc[2].kind == kFmtShift) { 351 return NewLIR3(opcode, r_dest_src1, r_src2, shift); 352 } else { 353 return NewLIR3(opcode, r_dest_src1, r_dest_src1, r_src2); 354 } 355 } else if (EncodingMap[opcode].flags & IS_QUAD_OP) { 356 return NewLIR4(opcode, r_dest_src1, r_dest_src1, r_src2, shift); 357 } else { 358 LOG(FATAL) << "Unexpected encoding operand count"; 359 return NULL; 360 } 361} 362 363LIR* ArmMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) { 364 return OpRegRegShift(op, r_dest_src1, r_src2, 0); 365} 366 367LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, int r_dest, int r_src1, 368 int r_src2, int shift) { 369 ArmOpcode opcode = kThumbBkpt; 370 bool thumb_form = (shift == 0) && ARM_LOWREG(r_dest) && ARM_LOWREG(r_src1) && 371 ARM_LOWREG(r_src2); 372 switch (op) { 373 case kOpAdd: 374 opcode = (thumb_form) ? kThumbAddRRR : kThumb2AddRRR; 375 break; 376 case kOpSub: 377 opcode = (thumb_form) ? kThumbSubRRR : kThumb2SubRRR; 378 break; 379 case kOpRsub: 380 opcode = kThumb2RsubRRR; 381 break; 382 case kOpAdc: 383 opcode = kThumb2AdcRRR; 384 break; 385 case kOpAnd: 386 opcode = kThumb2AndRRR; 387 break; 388 case kOpBic: 389 opcode = kThumb2BicRRR; 390 break; 391 case kOpXor: 392 opcode = kThumb2EorRRR; 393 break; 394 case kOpMul: 395 DCHECK_EQ(shift, 0); 396 opcode = kThumb2MulRRR; 397 break; 398 case kOpDiv: 399 DCHECK_EQ(shift, 0); 400 opcode = kThumb2SdivRRR; 401 break; 402 case kOpOr: 403 opcode = kThumb2OrrRRR; 404 break; 405 case kOpSbc: 406 opcode = kThumb2SbcRRR; 407 break; 408 case kOpLsl: 409 DCHECK_EQ(shift, 0); 410 opcode = kThumb2LslRRR; 411 break; 412 case kOpLsr: 413 DCHECK_EQ(shift, 0); 414 opcode = kThumb2LsrRRR; 415 break; 416 case kOpAsr: 417 DCHECK_EQ(shift, 0); 418 opcode = kThumb2AsrRRR; 419 break; 420 case kOpRor: 421 DCHECK_EQ(shift, 0); 422 opcode = kThumb2RorRRR; 423 break; 424 default: 425 LOG(FATAL) << "Bad opcode: " << op; 426 break; 427 } 428 DCHECK(!IsPseudoLirOp(opcode)); 429 if (EncodingMap[opcode].flags & IS_QUAD_OP) { 430 return NewLIR4(opcode, r_dest, r_src1, r_src2, shift); 431 } else { 432 DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP); 433 return NewLIR3(opcode, r_dest, r_src1, r_src2); 434 } 435} 436 437LIR* ArmMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) { 438 return OpRegRegRegShift(op, r_dest, r_src1, r_src2, 0); 439} 440 441LIR* ArmMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) { 442 LIR* res; 443 bool neg = (value < 0); 444 int32_t abs_value = (neg) ? -value : value; 445 ArmOpcode opcode = kThumbBkpt; 446 ArmOpcode alt_opcode = kThumbBkpt; 447 bool all_low_regs = (ARM_LOWREG(r_dest) && ARM_LOWREG(r_src1)); 448 int32_t mod_imm = ModifiedImmediate(value); 449 450 switch (op) { 451 case kOpLsl: 452 if (all_low_regs) 453 return NewLIR3(kThumbLslRRI5, r_dest, r_src1, value); 454 else 455 return NewLIR3(kThumb2LslRRI5, r_dest, r_src1, value); 456 case kOpLsr: 457 if (all_low_regs) 458 return NewLIR3(kThumbLsrRRI5, r_dest, r_src1, value); 459 else 460 return NewLIR3(kThumb2LsrRRI5, r_dest, r_src1, value); 461 case kOpAsr: 462 if (all_low_regs) 463 return NewLIR3(kThumbAsrRRI5, r_dest, r_src1, value); 464 else 465 return NewLIR3(kThumb2AsrRRI5, r_dest, r_src1, value); 466 case kOpRor: 467 return NewLIR3(kThumb2RorRRI5, r_dest, r_src1, value); 468 case kOpAdd: 469 if (ARM_LOWREG(r_dest) && (r_src1 == r13sp) && 470 (value <= 1020) && ((value & 0x3) == 0)) { 471 return NewLIR3(kThumbAddSpRel, r_dest, r_src1, value >> 2); 472 } else if (ARM_LOWREG(r_dest) && (r_src1 == r15pc) && 473 (value <= 1020) && ((value & 0x3) == 0)) { 474 return NewLIR3(kThumbAddPcRel, r_dest, r_src1, value >> 2); 475 } 476 // Note: intentional fallthrough 477 case kOpSub: 478 if (all_low_regs && ((abs_value & 0x7) == abs_value)) { 479 if (op == kOpAdd) 480 opcode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3; 481 else 482 opcode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3; 483 return NewLIR3(opcode, r_dest, r_src1, abs_value); 484 } else if ((abs_value & 0x3ff) == abs_value) { 485 if (op == kOpAdd) 486 opcode = (neg) ? kThumb2SubRRI12 : kThumb2AddRRI12; 487 else 488 opcode = (neg) ? kThumb2AddRRI12 : kThumb2SubRRI12; 489 return NewLIR3(opcode, r_dest, r_src1, abs_value); 490 } 491 if (mod_imm < 0) { 492 mod_imm = ModifiedImmediate(-value); 493 if (mod_imm >= 0) { 494 op = (op == kOpAdd) ? kOpSub : kOpAdd; 495 } 496 } 497 if (op == kOpSub) { 498 opcode = kThumb2SubRRI8M; 499 alt_opcode = kThumb2SubRRR; 500 } else { 501 opcode = kThumb2AddRRI8M; 502 alt_opcode = kThumb2AddRRR; 503 } 504 break; 505 case kOpRsub: 506 opcode = kThumb2RsubRRI8M; 507 alt_opcode = kThumb2RsubRRR; 508 break; 509 case kOpAdc: 510 opcode = kThumb2AdcRRI8M; 511 alt_opcode = kThumb2AdcRRR; 512 break; 513 case kOpSbc: 514 opcode = kThumb2SbcRRI8M; 515 alt_opcode = kThumb2SbcRRR; 516 break; 517 case kOpOr: 518 opcode = kThumb2OrrRRI8M; 519 alt_opcode = kThumb2OrrRRR; 520 break; 521 case kOpAnd: 522 if (mod_imm < 0) { 523 mod_imm = ModifiedImmediate(~value); 524 if (mod_imm >= 0) { 525 return NewLIR3(kThumb2BicRRI8M, r_dest, r_src1, mod_imm); 526 } 527 } 528 opcode = kThumb2AndRRI8M; 529 alt_opcode = kThumb2AndRRR; 530 break; 531 case kOpXor: 532 opcode = kThumb2EorRRI8M; 533 alt_opcode = kThumb2EorRRR; 534 break; 535 case kOpMul: 536 // TUNING: power of 2, shift & add 537 mod_imm = -1; 538 alt_opcode = kThumb2MulRRR; 539 break; 540 case kOpCmp: { 541 LIR* res; 542 if (mod_imm >= 0) { 543 res = NewLIR2(kThumb2CmpRI8M, r_src1, mod_imm); 544 } else { 545 mod_imm = ModifiedImmediate(-value); 546 if (mod_imm >= 0) { 547 res = NewLIR2(kThumb2CmnRI8M, r_src1, mod_imm); 548 } else { 549 int r_tmp = AllocTemp(); 550 res = LoadConstant(r_tmp, value); 551 OpRegReg(kOpCmp, r_src1, r_tmp); 552 FreeTemp(r_tmp); 553 } 554 } 555 return res; 556 } 557 default: 558 LOG(FATAL) << "Bad opcode: " << op; 559 } 560 561 if (mod_imm >= 0) { 562 return NewLIR3(opcode, r_dest, r_src1, mod_imm); 563 } else { 564 int r_scratch = AllocTemp(); 565 LoadConstant(r_scratch, value); 566 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP) 567 res = NewLIR4(alt_opcode, r_dest, r_src1, r_scratch, 0); 568 else 569 res = NewLIR3(alt_opcode, r_dest, r_src1, r_scratch); 570 FreeTemp(r_scratch); 571 return res; 572 } 573} 574 575/* Handle Thumb-only variants here - otherwise punt to OpRegRegImm */ 576LIR* ArmMir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) { 577 bool neg = (value < 0); 578 int32_t abs_value = (neg) ? -value : value; 579 bool short_form = (((abs_value & 0xff) == abs_value) && ARM_LOWREG(r_dest_src1)); 580 ArmOpcode opcode = kThumbBkpt; 581 switch (op) { 582 case kOpAdd: 583 if (!neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */ 584 DCHECK_EQ((value & 0x3), 0); 585 return NewLIR1(kThumbAddSpI7, value >> 2); 586 } else if (short_form) { 587 opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8; 588 } 589 break; 590 case kOpSub: 591 if (!neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */ 592 DCHECK_EQ((value & 0x3), 0); 593 return NewLIR1(kThumbSubSpI7, value >> 2); 594 } else if (short_form) { 595 opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8; 596 } 597 break; 598 case kOpCmp: 599 if (ARM_LOWREG(r_dest_src1) && short_form) { 600 opcode = (short_form) ? kThumbCmpRI8 : kThumbCmpRR; 601 } else if (ARM_LOWREG(r_dest_src1)) { 602 opcode = kThumbCmpRR; 603 } else { 604 short_form = false; 605 opcode = kThumbCmpHL; 606 } 607 break; 608 default: 609 /* Punt to OpRegRegImm - if bad case catch it there */ 610 short_form = false; 611 break; 612 } 613 if (short_form) { 614 return NewLIR2(opcode, r_dest_src1, abs_value); 615 } else { 616 return OpRegRegImm(op, r_dest_src1, r_dest_src1, value); 617 } 618} 619 620LIR* ArmMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) { 621 LIR* res = NULL; 622 int32_t val_lo = Low32Bits(value); 623 int32_t val_hi = High32Bits(value); 624 int target_reg = S2d(r_dest_lo, r_dest_hi); 625 if (ARM_FPREG(r_dest_lo)) { 626 if ((val_lo == 0) && (val_hi == 0)) { 627 // TODO: we need better info about the target CPU. a vector exclusive or 628 // would probably be better here if we could rely on its existance. 629 // Load an immediate +2.0 (which encodes to 0) 630 NewLIR2(kThumb2Vmovd_IMM8, target_reg, 0); 631 // +0.0 = +2.0 - +2.0 632 res = NewLIR3(kThumb2Vsubd, target_reg, target_reg, target_reg); 633 } else { 634 int encoded_imm = EncodeImmDouble(value); 635 if (encoded_imm >= 0) { 636 res = NewLIR2(kThumb2Vmovd_IMM8, target_reg, encoded_imm); 637 } 638 } 639 } else { 640 if ((InexpensiveConstantInt(val_lo) && (InexpensiveConstantInt(val_hi)))) { 641 res = LoadConstantNoClobber(r_dest_lo, val_lo); 642 LoadConstantNoClobber(r_dest_hi, val_hi); 643 } 644 } 645 if (res == NULL) { 646 // No short form - load from the literal pool. 647 LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); 648 if (data_target == NULL) { 649 data_target = AddWideData(&literal_list_, val_lo, val_hi); 650 } 651 if (ARM_FPREG(r_dest_lo)) { 652 res = RawLIR(current_dalvik_offset_, kThumb2Vldrd, 653 target_reg, r15pc, 0, 0, 0, data_target); 654 } else { 655 res = RawLIR(current_dalvik_offset_, kThumb2LdrdPcRel8, 656 r_dest_lo, r_dest_hi, r15pc, 0, 0, data_target); 657 } 658 SetMemRefType(res, true, kLiteral); 659 AppendLIR(res); 660 } 661 return res; 662} 663 664int ArmMir2Lir::EncodeShift(int code, int amount) { 665 return ((amount & 0x1f) << 2) | code; 666} 667 668LIR* ArmMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest, 669 int scale, OpSize size) { 670 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_dest); 671 LIR* load; 672 ArmOpcode opcode = kThumbBkpt; 673 bool thumb_form = (all_low_regs && (scale == 0)); 674 int reg_ptr; 675 676 if (ARM_FPREG(r_dest)) { 677 if (ARM_SINGLEREG(r_dest)) { 678 DCHECK((size == kWord) || (size == kSingle)); 679 opcode = kThumb2Vldrs; 680 size = kSingle; 681 } else { 682 DCHECK(ARM_DOUBLEREG(r_dest)); 683 DCHECK((size == kLong) || (size == kDouble)); 684 DCHECK_EQ((r_dest & 0x1), 0); 685 opcode = kThumb2Vldrd; 686 size = kDouble; 687 } 688 } else { 689 if (size == kSingle) 690 size = kWord; 691 } 692 693 switch (size) { 694 case kDouble: // fall-through 695 case kSingle: 696 reg_ptr = AllocTemp(); 697 if (scale) { 698 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index, 699 EncodeShift(kArmLsl, scale)); 700 } else { 701 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index); 702 } 703 load = NewLIR3(opcode, r_dest, reg_ptr, 0); 704 FreeTemp(reg_ptr); 705 return load; 706 case kWord: 707 opcode = (thumb_form) ? kThumbLdrRRR : kThumb2LdrRRR; 708 break; 709 case kUnsignedHalf: 710 opcode = (thumb_form) ? kThumbLdrhRRR : kThumb2LdrhRRR; 711 break; 712 case kSignedHalf: 713 opcode = (thumb_form) ? kThumbLdrshRRR : kThumb2LdrshRRR; 714 break; 715 case kUnsignedByte: 716 opcode = (thumb_form) ? kThumbLdrbRRR : kThumb2LdrbRRR; 717 break; 718 case kSignedByte: 719 opcode = (thumb_form) ? kThumbLdrsbRRR : kThumb2LdrsbRRR; 720 break; 721 default: 722 LOG(FATAL) << "Bad size: " << size; 723 } 724 if (thumb_form) 725 load = NewLIR3(opcode, r_dest, rBase, r_index); 726 else 727 load = NewLIR4(opcode, r_dest, rBase, r_index, scale); 728 729 return load; 730} 731 732LIR* ArmMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, 733 int scale, OpSize size) { 734 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_src); 735 LIR* store = NULL; 736 ArmOpcode opcode = kThumbBkpt; 737 bool thumb_form = (all_low_regs && (scale == 0)); 738 int reg_ptr; 739 740 if (ARM_FPREG(r_src)) { 741 if (ARM_SINGLEREG(r_src)) { 742 DCHECK((size == kWord) || (size == kSingle)); 743 opcode = kThumb2Vstrs; 744 size = kSingle; 745 } else { 746 DCHECK(ARM_DOUBLEREG(r_src)); 747 DCHECK((size == kLong) || (size == kDouble)); 748 DCHECK_EQ((r_src & 0x1), 0); 749 opcode = kThumb2Vstrd; 750 size = kDouble; 751 } 752 } else { 753 if (size == kSingle) 754 size = kWord; 755 } 756 757 switch (size) { 758 case kDouble: // fall-through 759 case kSingle: 760 reg_ptr = AllocTemp(); 761 if (scale) { 762 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index, 763 EncodeShift(kArmLsl, scale)); 764 } else { 765 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index); 766 } 767 store = NewLIR3(opcode, r_src, reg_ptr, 0); 768 FreeTemp(reg_ptr); 769 return store; 770 case kWord: 771 opcode = (thumb_form) ? kThumbStrRRR : kThumb2StrRRR; 772 break; 773 case kUnsignedHalf: 774 case kSignedHalf: 775 opcode = (thumb_form) ? kThumbStrhRRR : kThumb2StrhRRR; 776 break; 777 case kUnsignedByte: 778 case kSignedByte: 779 opcode = (thumb_form) ? kThumbStrbRRR : kThumb2StrbRRR; 780 break; 781 default: 782 LOG(FATAL) << "Bad size: " << size; 783 } 784 if (thumb_form) 785 store = NewLIR3(opcode, r_src, rBase, r_index); 786 else 787 store = NewLIR4(opcode, r_src, rBase, r_index, scale); 788 789 return store; 790} 791 792/* 793 * Load value from base + displacement. Optionally perform null check 794 * on base (which must have an associated s_reg and MIR). If not 795 * performing null check, incoming MIR can be null. 796 */ 797LIR* ArmMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest, 798 int r_dest_hi, OpSize size, int s_reg) { 799 LIR* load = NULL; 800 ArmOpcode opcode = kThumbBkpt; 801 bool short_form = false; 802 bool thumb2Form = (displacement < 4092 && displacement >= 0); 803 bool all_low_regs = (ARM_LOWREG(rBase) && ARM_LOWREG(r_dest)); 804 int encoded_disp = displacement; 805 bool is64bit = false; 806 bool already_generated = false; 807 switch (size) { 808 case kDouble: 809 case kLong: 810 is64bit = true; 811 if (ARM_FPREG(r_dest)) { 812 if (ARM_SINGLEREG(r_dest)) { 813 DCHECK(ARM_FPREG(r_dest_hi)); 814 r_dest = S2d(r_dest, r_dest_hi); 815 } 816 opcode = kThumb2Vldrd; 817 if (displacement <= 1020) { 818 short_form = true; 819 encoded_disp >>= 2; 820 } 821 break; 822 } else { 823 if (displacement <= 1020) { 824 load = NewLIR4(kThumb2LdrdI8, r_dest, r_dest_hi, rBase, displacement >> 2); 825 } else { 826 load = LoadBaseDispBody(rBase, displacement, r_dest, 827 -1, kWord, s_reg); 828 LoadBaseDispBody(rBase, displacement + 4, r_dest_hi, 829 -1, kWord, INVALID_SREG); 830 } 831 already_generated = true; 832 } 833 case kSingle: 834 case kWord: 835 if (ARM_FPREG(r_dest)) { 836 opcode = kThumb2Vldrs; 837 if (displacement <= 1020) { 838 short_form = true; 839 encoded_disp >>= 2; 840 } 841 break; 842 } 843 if (ARM_LOWREG(r_dest) && (rBase == r15pc) && 844 (displacement <= 1020) && (displacement >= 0)) { 845 short_form = true; 846 encoded_disp >>= 2; 847 opcode = kThumbLdrPcRel; 848 } else if (ARM_LOWREG(r_dest) && (rBase == r13sp) && 849 (displacement <= 1020) && (displacement >= 0)) { 850 short_form = true; 851 encoded_disp >>= 2; 852 opcode = kThumbLdrSpRel; 853 } else if (all_low_regs && displacement < 128 && displacement >= 0) { 854 DCHECK_EQ((displacement & 0x3), 0); 855 short_form = true; 856 encoded_disp >>= 2; 857 opcode = kThumbLdrRRI5; 858 } else if (thumb2Form) { 859 short_form = true; 860 opcode = kThumb2LdrRRI12; 861 } 862 break; 863 case kUnsignedHalf: 864 if (all_low_regs && displacement < 64 && displacement >= 0) { 865 DCHECK_EQ((displacement & 0x1), 0); 866 short_form = true; 867 encoded_disp >>= 1; 868 opcode = kThumbLdrhRRI5; 869 } else if (displacement < 4092 && displacement >= 0) { 870 short_form = true; 871 opcode = kThumb2LdrhRRI12; 872 } 873 break; 874 case kSignedHalf: 875 if (thumb2Form) { 876 short_form = true; 877 opcode = kThumb2LdrshRRI12; 878 } 879 break; 880 case kUnsignedByte: 881 if (all_low_regs && displacement < 32 && displacement >= 0) { 882 short_form = true; 883 opcode = kThumbLdrbRRI5; 884 } else if (thumb2Form) { 885 short_form = true; 886 opcode = kThumb2LdrbRRI12; 887 } 888 break; 889 case kSignedByte: 890 if (thumb2Form) { 891 short_form = true; 892 opcode = kThumb2LdrsbRRI12; 893 } 894 break; 895 default: 896 LOG(FATAL) << "Bad size: " << size; 897 } 898 899 if (!already_generated) { 900 if (short_form) { 901 load = NewLIR3(opcode, r_dest, rBase, encoded_disp); 902 } else { 903 int reg_offset = AllocTemp(); 904 LoadConstant(reg_offset, encoded_disp); 905 load = LoadBaseIndexed(rBase, reg_offset, r_dest, 0, size); 906 FreeTemp(reg_offset); 907 } 908 } 909 910 // TODO: in future may need to differentiate Dalvik accesses w/ spills 911 if (rBase == rARM_SP) { 912 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, is64bit); 913 } 914 return load; 915} 916 917LIR* ArmMir2Lir::LoadBaseDisp(int rBase, int displacement, int r_dest, 918 OpSize size, int s_reg) { 919 return LoadBaseDispBody(rBase, displacement, r_dest, -1, size, s_reg); 920} 921 922LIR* ArmMir2Lir::LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, 923 int r_dest_hi, int s_reg) { 924 return LoadBaseDispBody(rBase, displacement, r_dest_lo, r_dest_hi, kLong, s_reg); 925} 926 927 928LIR* ArmMir2Lir::StoreBaseDispBody(int rBase, int displacement, 929 int r_src, int r_src_hi, OpSize size) { 930 LIR* store = NULL; 931 ArmOpcode opcode = kThumbBkpt; 932 bool short_form = false; 933 bool thumb2Form = (displacement < 4092 && displacement >= 0); 934 bool all_low_regs = (ARM_LOWREG(rBase) && ARM_LOWREG(r_src)); 935 int encoded_disp = displacement; 936 bool is64bit = false; 937 bool already_generated = false; 938 switch (size) { 939 case kLong: 940 case kDouble: 941 is64bit = true; 942 if (!ARM_FPREG(r_src)) { 943 if (displacement <= 1020) { 944 store = NewLIR4(kThumb2StrdI8, r_src, r_src_hi, rBase, displacement >> 2); 945 } else { 946 store = StoreBaseDispBody(rBase, displacement, r_src, -1, kWord); 947 StoreBaseDispBody(rBase, displacement + 4, r_src_hi, -1, kWord); 948 } 949 already_generated = true; 950 } else { 951 if (ARM_SINGLEREG(r_src)) { 952 DCHECK(ARM_FPREG(r_src_hi)); 953 r_src = S2d(r_src, r_src_hi); 954 } 955 opcode = kThumb2Vstrd; 956 if (displacement <= 1020) { 957 short_form = true; 958 encoded_disp >>= 2; 959 } 960 } 961 break; 962 case kSingle: 963 case kWord: 964 if (ARM_FPREG(r_src)) { 965 DCHECK(ARM_SINGLEREG(r_src)); 966 opcode = kThumb2Vstrs; 967 if (displacement <= 1020) { 968 short_form = true; 969 encoded_disp >>= 2; 970 } 971 break; 972 } 973 if (ARM_LOWREG(r_src) && (rBase == r13sp) && 974 (displacement <= 1020) && (displacement >= 0)) { 975 short_form = true; 976 encoded_disp >>= 2; 977 opcode = kThumbStrSpRel; 978 } else if (all_low_regs && displacement < 128 && displacement >= 0) { 979 DCHECK_EQ((displacement & 0x3), 0); 980 short_form = true; 981 encoded_disp >>= 2; 982 opcode = kThumbStrRRI5; 983 } else if (thumb2Form) { 984 short_form = true; 985 opcode = kThumb2StrRRI12; 986 } 987 break; 988 case kUnsignedHalf: 989 case kSignedHalf: 990 if (all_low_regs && displacement < 64 && displacement >= 0) { 991 DCHECK_EQ((displacement & 0x1), 0); 992 short_form = true; 993 encoded_disp >>= 1; 994 opcode = kThumbStrhRRI5; 995 } else if (thumb2Form) { 996 short_form = true; 997 opcode = kThumb2StrhRRI12; 998 } 999 break; 1000 case kUnsignedByte: 1001 case kSignedByte: 1002 if (all_low_regs && displacement < 32 && displacement >= 0) { 1003 short_form = true; 1004 opcode = kThumbStrbRRI5; 1005 } else if (thumb2Form) { 1006 short_form = true; 1007 opcode = kThumb2StrbRRI12; 1008 } 1009 break; 1010 default: 1011 LOG(FATAL) << "Bad size: " << size; 1012 } 1013 if (!already_generated) { 1014 if (short_form) { 1015 store = NewLIR3(opcode, r_src, rBase, encoded_disp); 1016 } else { 1017 int r_scratch = AllocTemp(); 1018 LoadConstant(r_scratch, encoded_disp); 1019 store = StoreBaseIndexed(rBase, r_scratch, r_src, 0, size); 1020 FreeTemp(r_scratch); 1021 } 1022 } 1023 1024 // TODO: In future, may need to differentiate Dalvik & spill accesses 1025 if (rBase == rARM_SP) { 1026 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, is64bit); 1027 } 1028 return store; 1029} 1030 1031LIR* ArmMir2Lir::StoreBaseDisp(int rBase, int displacement, int r_src, 1032 OpSize size) { 1033 return StoreBaseDispBody(rBase, displacement, r_src, -1, size); 1034} 1035 1036LIR* ArmMir2Lir::StoreBaseDispWide(int rBase, int displacement, 1037 int r_src_lo, int r_src_hi) { 1038 return StoreBaseDispBody(rBase, displacement, r_src_lo, r_src_hi, kLong); 1039} 1040 1041LIR* ArmMir2Lir::OpFpRegCopy(int r_dest, int r_src) { 1042 int opcode; 1043 DCHECK_EQ(ARM_DOUBLEREG(r_dest), ARM_DOUBLEREG(r_src)); 1044 if (ARM_DOUBLEREG(r_dest)) { 1045 opcode = kThumb2Vmovd; 1046 } else { 1047 if (ARM_SINGLEREG(r_dest)) { 1048 opcode = ARM_SINGLEREG(r_src) ? kThumb2Vmovs : kThumb2Fmsr; 1049 } else { 1050 DCHECK(ARM_SINGLEREG(r_src)); 1051 opcode = kThumb2Fmrs; 1052 } 1053 } 1054 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src); 1055 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 1056 res->flags.is_nop = true; 1057 } 1058 return res; 1059} 1060 1061LIR* ArmMir2Lir::OpThreadMem(OpKind op, ThreadOffset thread_offset) { 1062 LOG(FATAL) << "Unexpected use of OpThreadMem for Arm"; 1063 return NULL; 1064} 1065 1066LIR* ArmMir2Lir::OpMem(OpKind op, int rBase, int disp) { 1067 LOG(FATAL) << "Unexpected use of OpMem for Arm"; 1068 return NULL; 1069} 1070 1071LIR* ArmMir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale, 1072 int displacement, int r_src, int r_src_hi, OpSize size, 1073 int s_reg) { 1074 LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for Arm"; 1075 return NULL; 1076} 1077 1078LIR* ArmMir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, int offset) { 1079 LOG(FATAL) << "Unexpected use of OpRegMem for Arm"; 1080 return NULL; 1081} 1082 1083LIR* ArmMir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, 1084 int displacement, int r_dest, int r_dest_hi, OpSize size, 1085 int s_reg) { 1086 LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for Arm"; 1087 return NULL; 1088} 1089 1090} // namespace art 1091