codegen_mips.h revision 0cd7ec2dcd8d7ba30bf3ca420b40dac52849876c 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
18#define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
19
20#include "dex/compiler_internals.h"
21#include "mips_lir.h"
22
23namespace art {
24
25class MipsMir2Lir : public Mir2Lir {
26  public:
27    MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen utilities.
30    bool SmallLiteralDivide(Instruction::Code dalvik_opcode, RegLocation rl_src,
31                                    RegLocation rl_dest, int lit);
32    int LoadHelper(int offset);
33    LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
34    LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
35                                  int s_reg);
36    LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37    LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
38                                     int r_dest, int r_dest_hi, OpSize size, int s_reg);
39    LIR* LoadConstantNoClobber(int r_dest, int value);
40    LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value);
41    LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42    LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
43    LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44    LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
45                                      int r_src, int r_src_hi, OpSize size, int s_reg);
46    void MarkGCCard(int val_reg, int tgt_addr_reg);
47
48    // Required for target - register utilities.
49    bool IsFpReg(int reg);
50    bool SameRegType(int reg1, int reg2);
51    int AllocTypedTemp(bool fp_hint, int reg_class);
52    int AllocTypedTempPair(bool fp_hint, int reg_class);
53    int S2d(int low_reg, int high_reg);
54    int TargetReg(SpecialTargetRegister reg);
55    RegisterInfo* GetRegInfo(int reg);
56    RegLocation GetReturnAlt();
57    RegLocation GetReturnWideAlt();
58    RegLocation LocCReturn();
59    RegLocation LocCReturnDouble();
60    RegLocation LocCReturnFloat();
61    RegLocation LocCReturnWide();
62    uint32_t FpRegMask();
63    uint64_t GetRegMaskCommon(int reg);
64    void AdjustSpillMask();
65    void ClobberCalleeSave();
66    void FlushReg(int reg);
67    void FlushRegWide(int reg1, int reg2);
68    void FreeCallTemps();
69    void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
70    void LockCallTemps();
71    void MarkPreservedSingle(int v_reg, int reg);
72    void CompilerInitializeRegAlloc();
73
74    // Required for target - miscellaneous.
75    AssemblerStatus AssembleInstructions(uintptr_t start_addr);
76    void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
77    void SetupTargetResourceMasks(LIR* lir);
78    const char* GetTargetInstFmt(int opcode);
79    const char* GetTargetInstName(int opcode);
80    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
81    uint64_t GetPCUseDefEncoding();
82    uint64_t GetTargetInstFlags(int opcode);
83    int GetInsnSize(LIR* lir);
84    bool IsUnconditionalBranch(LIR* lir);
85
86    // Required for target - Dalvik-level generators.
87    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
88                                   RegLocation rl_src1, RegLocation rl_src2);
89    void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index,
90                                RegLocation rl_src, int scale);
91    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
92                             RegLocation rl_index, RegLocation rl_dest, int scale);
93    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
94                             RegLocation rl_index, RegLocation rl_src, int scale);
95    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
96                                   RegLocation rl_src1, RegLocation rl_shift);
97    void GenMulLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
98    void GenAddLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
99    void GenAndLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
100    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
101                                  RegLocation rl_src1, RegLocation rl_src2);
102    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
103                                 RegLocation rl_src1, RegLocation rl_src2);
104    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105                          RegLocation rl_src2);
106    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
107    bool GenInlinedCas32(CallInfo* info, bool need_write_barrier);
108    bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
109    bool GenInlinedSqrt(CallInfo* info);
110    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
111    void GenOrLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
112    void GenSubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
113    void GenXorLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
114    LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
115                                ThrowKind kind);
116    RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div);
117    RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div);
118    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
119    void GenDivZeroCheck(int reg_lo, int reg_hi);
120    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
121    void GenExitSequence();
122    void GenFillArrayData(uint32_t table_offset, RegLocation rl_src);
123    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
124    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
125    void GenSelect(BasicBlock* bb, MIR* mir);
126    void GenMemBarrier(MemBarrierKind barrier_kind);
127    void GenMonitorEnter(int opt_flags, RegLocation rl_src);
128    void GenMonitorExit(int opt_flags, RegLocation rl_src);
129    void GenMoveException(RegLocation rl_dest);
130    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
131                                               int first_bit, int second_bit);
132    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
133    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
134    void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
135    void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
136    void GenSpecialCase(BasicBlock* bb, MIR* mir, SpecialCaseHandler special_case);
137
138    // Required for target - single operation generators.
139    LIR* OpUnconditionalBranch(LIR* target);
140    LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
141    LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
142    LIR* OpCondBranch(ConditionCode cc, LIR* target);
143    LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
144    LIR* OpFpRegCopy(int r_dest, int r_src);
145    LIR* OpIT(ConditionCode cond, const char* guide);
146    LIR* OpMem(OpKind op, int rBase, int disp);
147    LIR* OpPcRelLoad(int reg, LIR* target);
148    LIR* OpReg(OpKind op, int r_dest_src);
149    LIR* OpRegCopy(int r_dest, int r_src);
150    LIR* OpRegCopyNoInsert(int r_dest, int r_src);
151    LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
152    LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
153    LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
154    LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
155    LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2);
156    LIR* OpTestSuspend(LIR* target);
157    LIR* OpThreadMem(OpKind op, int thread_offset);
158    LIR* OpVldm(int rBase, int count);
159    LIR* OpVstm(int rBase, int count);
160    void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
161    void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi);
162    void OpTlsCmp(int offset, int val);
163
164    LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
165                          int s_reg);
166    LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size);
167    void SpillCoreRegs();
168    void UnSpillCoreRegs();
169    static const MipsEncodingMap EncodingMap[kMipsLast];
170    bool InexpensiveConstantInt(int32_t value);
171    bool InexpensiveConstantFloat(int32_t value);
172    bool InexpensiveConstantLong(int64_t value);
173    bool InexpensiveConstantDouble(int64_t value);
174
175  private:
176    void ConvertShortToLongBranch(LIR* lir);
177};
178
179}  // namespace art
180
181#endif  // ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
182